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Searched refs:TWI0_INT_STAT (Results 1 – 6 of 6) sorted by relevance

/arch/blackfin/mach-bf538/include/mach/
DdefBF538.h384 #define TWI0_INT_STAT 0xFFC01420 /* TWI0 Master Interrupt Register */ macro
397 #define TWI0_INT_SRC TWI0_INT_STAT
/arch/blackfin/mach-bf527/include/mach/
DdefBF522.h464 #define TWI0_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */ macro
/arch/blackfin/mach-bf518/include/mach/
DdefBF512.h464 #define TWI0_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */ macro
/arch/blackfin/mach-bf537/include/mach/
DdefBF534.h438 #define TWI0_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */ macro
/arch/blackfin/mach-bf548/include/mach/
DdefBF54x_base.h115 #define TWI0_INT_STAT 0xffc00720 /* TWI Interrupt Status Register */ macro
/arch/blackfin/mach-bf609/include/mach/
DdefBF60x_base.h604 #define TWI0_INT_STAT 0xFFC01E20 /* TWI0 Interrupt Status Register */ macro