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Searched refs:UART_FCR (Results 1 – 11 of 11) sorted by relevance

/arch/powerpc/platforms/embedded6xx/
Dls_uart.c78 out_8(avr_addr + UART_FCR, UART_FCR_ENABLE_FIFO); /* enable FIFO */ in avr_uart_configure()
97 out_8(avr_addr + UART_FCR, UART_FCR_ENABLE_FIFO); /* enable FIFO */ in ls_uart_init()
98 out_8(avr_addr + UART_FCR, UART_FCR_ENABLE_FIFO | in ls_uart_init()
100 out_8(avr_addr + UART_FCR, 0); in ls_uart_init()
/arch/frv/kernel/
Dgdb-io.h23 #undef UART_FCR
36 #define UART_FCR 2*8 /* Out: FIFO Control Register */ macro
/arch/powerpc/boot/
Dns16550.c20 #define UART_FCR 2 /* Out: FIFO Control Register */ macro
34 out_8(reg_base + (UART_FCR << reg_shift), 0x06); in ns16550_open()
Dvirtex.c18 #define UART_FCR 2 /* Out: FIFO Control Register */ macro
71 out_8(reg_base + (UART_FCR << reg_shift), in virtex_ns16550_console_init()
/arch/mips/jz4740/
Dserial.c23 case UART_FCR: in jz4740_serial_out()
/arch/powerpc/kernel/
Dudbg_16550.c23 #define UART_FCR 2 macro
30 #define UART_IIR UART_FCR
125 udbg_uart_out(UART_FCR, 0x7); in udbg_uart_setup()
/arch/x86/platform/intel-mid/
Dearly_printk_intel_mid.c265 writeb(0x0, phsu + UART_FCR); in hsu_early_console_init()
275 writeb(0x7, phsu + UART_FCR); in hsu_early_console_init()
285 writeb(0x7, phsu + UART_FCR); in hsu_early_console_init()
/arch/mn10300/unit-asb2303/include/unit/
Dserial.h71 #define GDBPORT_SERIAL_FCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_FCR * 4, u8)
86 #define GDBPORT_SERIAL_FCR __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_FCR * 4, u8)
/arch/sh/include/asm/
Dsmc37c93x.h60 #define UART_FCR 0x4 /* FIFO Control Register (Write Only) */ macro
/arch/mn10300/unit-asb2364/include/unit/
Dserial.h68 #define GDBPORT_SERIAL_FCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_FCR * 2, u8)
/arch/mn10300/unit-asb2305/include/unit/
Dserial.h62 #define GDBPORT_SERIAL_FCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_FCR * 4, u8)