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Searched refs:UVH_GR1_TLB_INT0_CONFIG_VECTOR_MASK (Results 1 – 2 of 2) sorted by relevance

/arch/ia64/include/asm/uv/
Duv_mmrs.h327 #define UVH_GR1_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL macro
/arch/x86/include/asm/uv/
Duv_mmrs.h935 #define UVH_GR1_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL macro