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/arch/frv/include/asm/
Dbusctl-regs.h24 #define __set_LGCR(V) do { *(volatile unsigned long *)(0xfe000010) = (V); } while(0) argument
25 #define __set_LMAICR(V) do { *(volatile unsigned long *)(0xfe000030) = (V); } while(0) argument
26 #define __set_LEMBR(V) do { *(volatile unsigned long *)(0xfe000040) = (V); } while(0) argument
27 #define __set_LEMAM(V) do { *(volatile unsigned long *)(0xfe000048) = (V); } while(0) argument
28 #define __set_LCR(R,V) do { *(volatile unsigned long *)(0xfe000100 + 8*(R)) = (V); } while(0) argument
29 #define __set_LSBR(R,V) do { *(volatile unsigned long *)(0xfe000c00 + 8*(R)) = (V); } while(0) argument
30 #define __set_LSAM(R,V) do { *(volatile unsigned long *)(0xfe000d00 + 8*(R)) = (V); } while(0) argument
Dmb93493-regs.h21 #define __set_MB93493(X,V) \ argument
23 *(volatile unsigned long *)(__region_CS3 + (X)) = (V); mb(); \
27 #define __set_MB93493_STSR(X,V) __set_MB93493(0x3c0 + (X) * 4, (V)) argument
32 #define __set_MB93493_IQSR(X,V) __set_MB93493(0x3d0 + (X) * 4, (V)) argument
35 #define __set_MB93493_DQSR(X,V) __set_MB93493(0x3e0 + (X) * 4, (V)) argument
38 #define __set_MB93493_LBSER(V) __set_MB93493(0x3f0, (V)) argument
50 #define __set_MB93493_LBSR(V) __set_MB93493(0x3fc, (V)) argument
56 #define __set_MB93493_VDC(X,V) __set_MB93493(MB93493_VDC_##X, (V)) argument
94 #define __set_MB93493_VCC(X,V) __set_MB93493(MB93493_VCC_##X, (V)) argument
179 #define __set_MB93493_I2C(port,X,V) __set_MB93493(MB93493_I2C_##X + ((port)*0x20), (V)) argument
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Dserial-regs.h24 #define __set_UART0(R,V) do { __reg(UART0_BASE + (R) * 8) = (V) << 24; } while(0) argument
25 #define __set_UART1(R,V) do { __reg(UART1_BASE + (R) * 8) = (V) << 24; } while(0) argument
30 #define __set_UART0_IER(V) __set_UART0(UART_IER,(V)) argument
31 #define __set_UART1_IER(V) __set_UART1(UART_IER,(V)) argument
35 #define __set_UCPSR(V) do { *(volatile unsigned long *)(0xfeff9c90) = (V); } while(0) argument
41 #define __set_UCPVR(V) do { *(volatile unsigned long *)(0xfeff9c98) = (V) << 24; mb(); } while(0) argument
Dtimer-regs.h51 #define __set_TCTR(V) do { *(volatile unsigned long *)(0xfeff9418) = (V); mb(); } while(0) argument
52 #define __set_TPRV(V) do { *(volatile unsigned long *)(0xfeff9420) = (V) << 24; mb(); } while(0) argument
53 #define __set_TPRCKSL(V) do { *(volatile unsigned long *)(0xfeff9428) = (V); mb(); } while(0) argument
54 #define __set_TCSR(T,V) \ argument
55 do { *(volatile unsigned long *)(0xfeff9400 + 8 * (T)) = (V); mb(); } while(0)
57 #define __set_TxCKSL(T,V) \ argument
58 do { *(volatile unsigned long *)(0xfeff9430 + 8 * (T)) = (V); mb(); } while(0)
60 #define __set_TCSR_DATA(T,V) __set_TCSR(T, (V) << 24) argument
61 #define __set_TxCKSL_DATA(T,V) __set_TxCKSL(T, TxCKSL_EIGHT | __TxCKSL_SELECT((V))) argument
Dgpio-regs.h18 #define __set_PDR(V) do { __reg(0xfeff0400) = (V); mb(); } while(0) argument
21 #define __set_GPDR(V) do { __reg(0xfeff0408) = (V); mb(); } while(0) argument
24 #define __set_SIR(V) do { __reg(0xfeff0410) = (V); mb(); } while(0) argument
27 #define __set_SOR(V) do { __reg(0xfeff0418) = (V); mb(); } while(0) argument
29 #define __set_PDSR(V) do { __reg(0xfeff0420) = (V); mb(); } while(0) argument
31 #define __set_PDCR(V) do { __reg(0xfeff0428) = (V); mb(); } while(0) argument
34 #define __set_RSTR(V) do { __reg(0xfeff0500) = (V); mb(); } while(0) argument
Dirc-regs.h19 #define __set_TM1(V) do { __reg(0xfeff9808) = (V); mb(); } while(0) argument
21 #define __set_TM1x(XI,V) \ argument
26 tm1 |= (V) << shift; \
47 #define __set_IRR(N,V) do { __reg(0xfeff9840 + (N) * 8) = (V); } while(0) argument
50 #define __set_IITMR(N,V) do { __reg(0xfeff9880 + (N) * 8) = (V); } while(0) argument
Dspr-regs.h59 #define __set_PSR(V) do { asm volatile("movgs %0,psr" : : "r"(V)); } while(0) argument
159 #define __set_HSR(R,V) do { asm volatile("movgs %0,hsr"#R : : "r"(V)); } while(0)
333 #define __set_IAMPR(R,V) do { asm volatile("movgs %0,iampr"#R : : "r"(V)); } while(0)
334 #define __set_DAMPR(R,V) do { asm volatile("movgs %0,dampr"#R : : "r"(V)); } while(0)
336 #define __set_IAMLR(R,V) do { asm volatile("movgs %0,iamlr"#R : : "r"(V)); } while(0)
337 #define __set_DAMLR(R,V) do { asm volatile("movgs %0,damlr"#R : : "r"(V)); } while(0)
Dspinlock.h15 #error no spinlocks for FR-V yet
/arch/powerpc/lib/
Dxor_vmx.c29 #define DEFINE(V) \ argument
30 unative_t *V = (unative_t *)V##_in; \
31 unative_t V##_0, V##_1, V##_2, V##_3
33 #define LOAD(V) \ argument
35 V##_0 = V[0]; \
36 V##_1 = V[1]; \
37 V##_2 = V[2]; \
38 V##_3 = V[3]; \
41 #define STORE(V) \ argument
43 V[0] = V##_0; \
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/arch/m68k/fpsp040/
Dslogn.S384 fmulx %fp2,%fp2 | ...FP2 IS V=U*U
388 |--U + V*(A1+U*(A2+U*(A3+U*(A4+U*(A5+U*A6))))) WHICH IS
389 |--[U + V*(A1+V*(A3+V*A5))] + [U*V*(A2+V*(A4+V*A6))]
394 fmuld LOGA6,%fp1 | ...V*A6
395 fmuld LOGA5,%fp2 | ...V*A5
397 faddd LOGA4,%fp1 | ...A4+V*A6
398 faddd LOGA3,%fp2 | ...A3+V*A5
400 fmulx %fp3,%fp1 | ...V*(A4+V*A6)
401 fmulx %fp3,%fp2 | ...V*(A3+V*A5)
403 faddd LOGA2,%fp1 | ...A2+V*(A4+V*A6)
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Dsatan.S317 |--U + A1*U*V*(A2 + V*(A3 + V)), V = U*U
319 |--THE NATURAL FORM IS U + U*V*(A1 + V*(A2 + V*A3))
322 |--PARTS A1*U*V AND (A2 + ... STUFF) MORE LOAD-BALANCED
328 faddx %fp1,%fp2 | ...A3+V
329 fmulx %fp1,%fp2 | ...V*(A3+V)
330 fmulx %fp0,%fp1 | ...U*V
331 faddd ATANA2,%fp2 | ...A2+V*(A3+V)
332 fmuld ATANA1,%fp1 | ...A1*U*V
333 fmulx %fp2,%fp1 | ...A1*U*V*(A2+V*(A3+V))
/arch/arm/boot/dts/
Ds5pv210-aquila.dts46 regulator-name = "V_TF_2.8V";
94 regulator-name = "VALIVE_1.1V";
101 regulator-name = "VUSB+MIPI_1.1V";
108 regulator-name = "VADC_3.3V";
114 regulator-name = "VTF_2.8V";
121 regulator-name = "VCC_3.3V";
128 regulator-name = "VCC_3.0V";
136 regulator-name = "VUSB+VDAC_3.3V";
143 regulator-name = "VCC+VCAM_2.8V";
150 regulator-name = "VPLL_1.1V";
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Dexynos4412-odroid-common.dtsi158 regulator-name = "VDD_ALIVE_1.0V";
165 regulator-name = "VDDQ_M1_2_1.8V";
172 regulator-name = "VDDQ_EXT_1.8V";
179 regulator-name = "VDDQ_MMC2_2.8V";
187 regulator-name = "VDDQ_MMC1_3_1.8V";
195 regulator-name = "VDD10_MPLL_1.0V";
202 regulator-name = "VDD10_XPLL_1.0V";
209 regulator-name = "VDD18_ABB1_1.8V";
216 regulator-name = "VDD33_USB_3.3V";
224 regulator-name = "VDDQ_C2C_W_1.8V";
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Dexynos4210-origen.dts44 regulator-name = "VMEM_VDD_2.8V";
125 regulator-name = "VDD_ABB_3.3V";
131 regulator-name = "VDD_ALIVE_1.1V";
138 regulator-name = "VMIPI_1.1V";
144 regulator-name = "VDD_RTC_1.8V";
151 regulator-name = "VMIPI_1.8V";
158 regulator-name = "VDD_AUD_1.8V";
164 regulator-name = "VADC_3.3V";
170 regulator-name = "DVDD_SWB_2.8V";
177 regulator-name = "VDD_PLL_1.1V";
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Ds5pv210-goni.dts46 regulator-name = "V_TF_2.8V";
105 regulator-name = "VALIVE_1.1V";
112 regulator-name = "VUSB+MIPI_1.1V";
119 regulator-name = "VADC_3.3V";
125 regulator-name = "VTF_2.8V";
131 regulator-name = "VCC_3.3V";
137 regulator-name = "VLCD_1.8V";
144 regulator-name = "VUSB+VDAC_3.3V";
150 regulator-name = "VCC+VCAM_2.8V";
156 regulator-name = "VPLL_1.1V";
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Dexynos4210-universal_c210.dts243 regulator-name = "VALIVE_1.2V";
250 regulator-name = "VUSB+MIPI_1.1V";
257 regulator-name = "VADC_3.3V";
263 regulator-name = "VTF_2.8V";
275 regulator-name = "VLCD+VMIPI_1.8V";
281 regulator-name = "VUSB+VDAC_3.3V";
288 regulator-name = "VCC_2.8V";
295 regulator-name = "VPLL_1.1V";
303 regulator-name = "CAM_AF_3.3V";
309 regulator-name = "PS_2.8V";
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Dexynos5250-arndale.dts81 regulator-name = "VDD_ALIVE_1.0V";
90 regulator-name = "VDD_28IO_DP_1.35V";
99 regulator-name = "VDD_COMMON1_1.8V";
108 regulator-name = "VDD_IOPERI_1.8V";
116 regulator-name = "VDD_EXT_1.8V";
125 regulator-name = "VDD_MPLL_1.1V";
134 regulator-name = "VDD_XPLL_1.1V";
143 regulator-name = "VDD_COMMON2_1.0V";
152 regulator-name = "VDD_33ON_3.0V";
159 regulator-name = "VDD_COMMON3_1.8V";
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Dexynos4412-trats2.dts59 regulator-name = "VMEM_VDD_2.8V";
77 regulator-name = "LCD_VDD_2.2V";
105 regulator-name = "LED_A_3.0V";
285 regulator-name = "VMIPI_1.0V";
293 regulator-name = "CAM_ISP_MIPI_1.2V";
301 regulator-name = "VMIPI_1.8V";
309 regulator-name = "VABB1_1.95V";
318 regulator-name = "VUOTG_3.0V";
326 regulator-name = "NFC_AVDD_1.8V";
334 regulator-name = "VABB2_1.95V";
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Dste-href.dtsi231 regulator-name = "V-DISPLAY";
235 regulator-name = "V-eMMC1";
239 regulator-name = "V-MMC-SD";
243 regulator-name = "V-INTCORE";
247 regulator-name = "V-TVOUT";
255 regulator-name = "V-AUD";
259 regulator-name = "V-AMIC1";
263 regulator-name = "V-AMIC2";
267 regulator-name = "V-DMIC";
271 regulator-name = "V-CSI/DSI";
Dsh73a0-kzm9g-reference.dts52 regulator-name = "fixed-1.8V";
61 regulator-name = "fixed-3.3V";
188 regulator-name = "1.315V CPU";
195 regulator-name = "1.8V";
202 regulator-name = "1.215V";
209 regulator-name = "2.8V CPU";
216 regulator-name = "3.0V CPU";
223 regulator-name = "2.8V";
230 regulator-name = "2.8V #2";
237 regulator-name = "1.15V CPU";
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Dda850-evm.dts62 /* Derived from VBAT: Baseboard 3.3V / 1.8V */
184 regulator-name = "VDCDC1_3.3V";
192 regulator-name = "VDCDC2_3.3V";
201 regulator-name = "VDCDC3_1.2V";
210 regulator-name = "LDO1_1.8V";
218 regulator-name = "LDO2_1.2V";
Dexynos4210-trats.dts38 regulator-name = "VMEM_VDD_2.8V";
83 regulator-name = "VT_CORE_1.5V";
233 regulator-name = "VMIPI_1.8V";
246 regulator-name = "CAM_ISP_1.8V";
272 regulator-name = "VT_CAM_1.8V";
284 regulator-name = "VLCD_2.2V";
290 regulator-name = "CAM_SENSOR_IO_1.8V";
296 regulator-name = "VDDQ_M1M2_1.2V";
322 regulator-name = "CAM_ISP_CORE_1.2V";
335 regulator-name = "VCC_SUB_2.0V";
Dste-snowball.dts358 regulator-name = "V-DISPLAY";
362 regulator-name = "V-eMMC1";
366 regulator-name = "V-MMC-SD";
370 regulator-name = "V-INTCORE";
374 regulator-name = "V-TVOUT";
382 regulator-name = "V-AUD";
386 regulator-name = "V-AMIC1";
390 regulator-name = "V-AMIC2";
394 regulator-name = "V-DMIC";
398 regulator-name = "V-CSI/DSI";
/arch/frv/mb93090-mb00/
Dpci-vdk.c66 #define __set_PciCfgDataB(A,V) \ argument
67 writeb((V), (volatile void __iomem *) __region_CS1 + 0x88 + (3 - ((A) & 3)))
69 #define __set_PciCfgDataW(A,V) \ argument
70 writew((V), (volatile void __iomem *) __region_CS1 + 0x88 + (2 - ((A) & 2)))
72 #define __set_PciCfgDataL(A,V) \ argument
73 writel((V), (volatile void __iomem *) __region_CS1 + 0x88)
79 #define __set_PciBridgeDataB(A,V) writeb((V), (volatile void __iomem *) __region_CS1 + 0x800 + (A)) argument
80 #define __set_PciBridgeDataW(A,V) writew((V), (volatile void __iomem *) __region_CS1 + 0x800 + (A)) argument
81 #define __set_PciBridgeDataL(A,V) writel((V), (volatile void __iomem *) __region_CS1 + 0x800 + (A)) argument
/arch/mips/cavium-octeon/executive/
Dcvmx-l2c.c473 if (tag.s.V && (tag.s.addr == tag_addr)) { in cvmx_l2c_unlock_line()
490 if (tag.s.V && (tag.s.addr == tag_addr)) { in cvmx_l2c_unlock_line()
523 uint64_t V:1; /* Line valid */ member
531 uint64_t V:1; /* Line valid */ member
539 uint64_t V:1; /* Line valid */ member
547 uint64_t V:1; /* Line valid */ member
555 uint64_t V:1; /* Line valid */ member
667 tag.s.V = l2c_tadx_tag.s.valid; in cvmx_l2c_get_tag()
682 tag.s.V = tmp_tag.cn58xx.V; in cvmx_l2c_get_tag()
688 tag.s.V = tmp_tag.cn38xx.V; in cvmx_l2c_get_tag()
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