Searched refs:VADDR (Results 1 – 4 of 4) sorted by relevance
| /arch/sparc/include/asm/ |
| D | tsb.h | 155 #define KERN_PGTABLE_WALK(VADDR, REG1, REG2, FAIL_LABEL) \ argument
158 sllx VADDR, 64 - (PGDIR_SHIFT + PGDIR_BITS), REG2; \
163 sllx VADDR, 64 - (PUD_SHIFT + PUD_BITS), REG2; \
175 sllx VADDR, 64 - (PMD_SHIFT + PMD_BITS), REG2; \
187 and VADDR, REG2, REG2; \
190 698: sllx VADDR, 64 - PMD_SHIFT, REG2; \
207 #define USER_PGTABLE_CHECK_PMD_HUGE(VADDR, REG1, REG2, FAIL_LABEL, PTE_LABEL) \ argument
216 and VADDR, REG2, REG2; \
221 #define USER_PGTABLE_CHECK_PMD_HUGE(VADDR, REG1, REG2, FAIL_LABEL, PTE_LABEL) \ argument
235 #define USER_PGTABLE_WALK_TL1(VADDR, PHYS_PGD, REG1, REG2, FAIL_LABEL) \ argument
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| D | pgtsrmmu.h | 147 #define __nocache_pa(VADDR) (((unsigned long)VADDR) - SRMMU_NOCACHE_VADDR + __pa((unsigned long)srm… argument
149 #define __nocache_fix(VADDR) __va(__nocache_pa(VADDR)) argument
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| /arch/sparc/kernel/ |
| D | sun4v_tlb_miss.S | 10 #define LOAD_ITLB_INFO(BASE, VADDR, CTX) \ argument
11 ldx [BASE + HV_FAULT_I_ADDR_OFFSET], VADDR; \
15 #define LOAD_DTLB_INFO(BASE, VADDR, CTX) \ argument
16 ldx [BASE + HV_FAULT_D_ADDR_OFFSET], VADDR; \
23 #define COMPUTE_TAG_TARGET(DEST, VADDR, CTX, ZERO_CTX_LABEL) \ argument
24 srlx VADDR, 22, DEST; \
35 #define COMPUTE_TSB_PTR(TSB_PTR, VADDR, HASH_SHIFT, TMP1, TMP2) \ argument
40 srlx VADDR, HASH_SHIFT, TMP1; \
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| D | trampoline_64.S | 161 stx %g2, [%sp + 2047 + 128 + 0x28] ! VADDR
194 stx %g2, [%sp + 2047 + 128 + 0x28] ! VADDR
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