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Searched refs:XCHAL_ICACHE_SIZE (Results 1 – 7 of 7) sorted by relevance

/arch/xtensa/include/asm/
Dcache.h21 #define ICACHE_WAY_SIZE (XCHAL_ICACHE_SIZE/XCHAL_ICACHE_WAYS)
Dcacheasm.h86 __loop_cache_all \ar \at iiu XCHAL_ICACHE_SIZE XCHAL_ICACHE_LINEWIDTH
/arch/xtensa/variants/fsf/include/variant/
Dcore.h119 #define XCHAL_ICACHE_SIZE 8192 /* I-cache size in bytes or 0 */ macro
/arch/xtensa/variants/dc232b/include/variant/
Dcore.h126 #define XCHAL_ICACHE_SIZE 16384 /* I-cache size in bytes or 0 */ macro
/arch/xtensa/variants/s6000/include/variant/
Dcore.h125 #define XCHAL_ICACHE_SIZE 32768 /* I-cache size in bytes or 0 */ macro
/arch/xtensa/variants/dc233c/include/variant/
Dcore.h165 #define XCHAL_ICACHE_SIZE 16384 /* I-cache size in bytes or 0 */ macro
/arch/xtensa/kernel/
Dsetup.c695 XCHAL_ICACHE_SIZE, in c_show()