1 /*
2 * S390 version
3 * Copyright IBM Corp. 1999
4 * Author(s): Hartmut Penner (hp@de.ibm.com),
5 * Martin Schwidefsky (schwidefsky@de.ibm.com)
6 *
7 * Derived from "include/asm-i386/processor.h"
8 * Copyright (C) 1994, Linus Torvalds
9 */
10
11 #ifndef __ASM_S390_PROCESSOR_H
12 #define __ASM_S390_PROCESSOR_H
13
14 #define CIF_MCCK_PENDING 0 /* machine check handling is pending */
15 #define CIF_ASCE 1 /* user asce needs fixup / uaccess */
16 #define CIF_NOHZ_DELAY 2 /* delay HZ disable for a tick */
17
18 #define _CIF_MCCK_PENDING (1<<CIF_MCCK_PENDING)
19 #define _CIF_ASCE (1<<CIF_ASCE)
20 #define _CIF_NOHZ_DELAY (1<<CIF_NOHZ_DELAY)
21
22
23 #ifndef __ASSEMBLY__
24
25 #include <linux/linkage.h>
26 #include <linux/irqflags.h>
27 #include <asm/cpu.h>
28 #include <asm/page.h>
29 #include <asm/ptrace.h>
30 #include <asm/setup.h>
31 #include <asm/runtime_instr.h>
32
set_cpu_flag(int flag)33 static inline void set_cpu_flag(int flag)
34 {
35 S390_lowcore.cpu_flags |= (1U << flag);
36 }
37
clear_cpu_flag(int flag)38 static inline void clear_cpu_flag(int flag)
39 {
40 S390_lowcore.cpu_flags &= ~(1U << flag);
41 }
42
test_cpu_flag(int flag)43 static inline int test_cpu_flag(int flag)
44 {
45 return !!(S390_lowcore.cpu_flags & (1U << flag));
46 }
47
48 #define arch_needs_cpu() test_cpu_flag(CIF_NOHZ_DELAY)
49
50 /*
51 * Default implementation of macro that returns current
52 * instruction pointer ("program counter").
53 */
54 #define current_text_addr() ({ void *pc; asm("basr %0,0" : "=a" (pc)); pc; })
55
get_cpu_id(struct cpuid * ptr)56 static inline void get_cpu_id(struct cpuid *ptr)
57 {
58 asm volatile("stidp %0" : "=Q" (*ptr));
59 }
60
61 extern void s390_adjust_jiffies(void);
62 extern const struct seq_operations cpuinfo_op;
63 extern int sysctl_ieee_emulation_warnings;
64 extern void execve_tail(void);
65
66 /*
67 * User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit.
68 */
69 #ifndef CONFIG_64BIT
70
71 #define TASK_SIZE (1UL << 31)
72 #define TASK_MAX_SIZE (1UL << 31)
73 #define TASK_UNMAPPED_BASE (1UL << 30)
74
75 #else /* CONFIG_64BIT */
76
77 #define TASK_SIZE_OF(tsk) ((tsk)->mm ? \
78 (tsk)->mm->context.asce_limit : TASK_MAX_SIZE)
79 #define TASK_UNMAPPED_BASE (test_thread_flag(TIF_31BIT) ? \
80 (1UL << 30) : (1UL << 41))
81 #define TASK_SIZE TASK_SIZE_OF(current)
82 #define TASK_MAX_SIZE (1UL << 53)
83
84 #endif /* CONFIG_64BIT */
85
86 #ifndef CONFIG_64BIT
87 #define STACK_TOP (1UL << 31)
88 #define STACK_TOP_MAX (1UL << 31)
89 #else /* CONFIG_64BIT */
90 #define STACK_TOP (1UL << (test_thread_flag(TIF_31BIT) ? 31:42))
91 #define STACK_TOP_MAX (1UL << 42)
92 #endif /* CONFIG_64BIT */
93
94 #define HAVE_ARCH_PICK_MMAP_LAYOUT
95
96 typedef struct {
97 __u32 ar4;
98 } mm_segment_t;
99
100 /*
101 * Thread structure
102 */
103 struct thread_struct {
104 s390_fp_regs fp_regs;
105 unsigned int acrs[NUM_ACRS];
106 unsigned long ksp; /* kernel stack pointer */
107 mm_segment_t mm_segment;
108 unsigned long gmap_addr; /* address of last gmap fault. */
109 unsigned int gmap_pfault; /* signal of a pending guest pfault */
110 struct per_regs per_user; /* User specified PER registers */
111 struct per_event per_event; /* Cause of the last PER trap */
112 unsigned long per_flags; /* Flags to control debug behavior */
113 /* pfault_wait is used to block the process on a pfault event */
114 unsigned long pfault_wait;
115 struct list_head list;
116 /* cpu runtime instrumentation */
117 struct runtime_instr_cb *ri_cb;
118 int ri_signum;
119 #ifdef CONFIG_64BIT
120 unsigned char trap_tdb[256]; /* Transaction abort diagnose block */
121 __vector128 *vxrs; /* Vector register save area */
122 #endif
123 };
124
125 /* Flag to disable transactions. */
126 #define PER_FLAG_NO_TE 1UL
127 /* Flag to enable random transaction aborts. */
128 #define PER_FLAG_TE_ABORT_RAND 2UL
129 /* Flag to specify random transaction abort mode:
130 * - abort each transaction at a random instruction before TEND if set.
131 * - abort random transactions at a random instruction if cleared.
132 */
133 #define PER_FLAG_TE_ABORT_RAND_TEND 4UL
134
135 typedef struct thread_struct thread_struct;
136
137 /*
138 * Stack layout of a C stack frame.
139 */
140 #ifndef __PACK_STACK
141 struct stack_frame {
142 unsigned long back_chain;
143 unsigned long empty1[5];
144 unsigned long gprs[10];
145 unsigned int empty2[8];
146 };
147 #else
148 struct stack_frame {
149 unsigned long empty1[5];
150 unsigned int empty2[8];
151 unsigned long gprs[10];
152 unsigned long back_chain;
153 };
154 #endif
155
156 #define ARCH_MIN_TASKALIGN 8
157
158 #define INIT_THREAD { \
159 .ksp = sizeof(init_stack) + (unsigned long) &init_stack, \
160 }
161
162 /*
163 * Do necessary setup to start up a new thread.
164 */
165 #define start_thread(regs, new_psw, new_stackp) do { \
166 regs->psw.mask = PSW_USER_BITS | PSW_MASK_EA | PSW_MASK_BA; \
167 regs->psw.addr = new_psw | PSW_ADDR_AMODE; \
168 regs->gprs[15] = new_stackp; \
169 execve_tail(); \
170 } while (0)
171
172 #define start_thread31(regs, new_psw, new_stackp) do { \
173 regs->psw.mask = PSW_USER_BITS | PSW_MASK_BA; \
174 regs->psw.addr = new_psw | PSW_ADDR_AMODE; \
175 regs->gprs[15] = new_stackp; \
176 crst_table_downgrade(current->mm, 1UL << 31); \
177 execve_tail(); \
178 } while (0)
179
180 /* Forward declaration, a strange C thing */
181 struct task_struct;
182 struct mm_struct;
183 struct seq_file;
184
185 #ifdef CONFIG_64BIT
186 extern void show_cacheinfo(struct seq_file *m);
187 #else
show_cacheinfo(struct seq_file * m)188 static inline void show_cacheinfo(struct seq_file *m) { }
189 #endif
190
191 /* Free all resources held by a thread. */
192 extern void release_thread(struct task_struct *);
193
194 /*
195 * Return saved PC of a blocked thread.
196 */
197 extern unsigned long thread_saved_pc(struct task_struct *t);
198
199 unsigned long get_wchan(struct task_struct *p);
200 #define task_pt_regs(tsk) ((struct pt_regs *) \
201 (task_stack_page(tsk) + THREAD_SIZE) - 1)
202 #define KSTK_EIP(tsk) (task_pt_regs(tsk)->psw.addr)
203 #define KSTK_ESP(tsk) (task_pt_regs(tsk)->gprs[15])
204
205 /* Has task runtime instrumentation enabled ? */
206 #define is_ri_task(tsk) (!!(tsk)->thread.ri_cb)
207
stap(void)208 static inline unsigned short stap(void)
209 {
210 unsigned short cpu_address;
211
212 asm volatile("stap %0" : "=m" (cpu_address));
213 return cpu_address;
214 }
215
216 /*
217 * Give up the time slice of the virtual PU.
218 */
cpu_relax(void)219 static inline void cpu_relax(void)
220 {
221 if (MACHINE_HAS_DIAG44)
222 asm volatile("diag 0,0,68");
223 barrier();
224 }
225
226 #define cpu_relax_lowlatency() barrier()
227
psw_set_key(unsigned int key)228 static inline void psw_set_key(unsigned int key)
229 {
230 asm volatile("spka 0(%0)" : : "d" (key));
231 }
232
233 /*
234 * Set PSW to specified value.
235 */
__load_psw(psw_t psw)236 static inline void __load_psw(psw_t psw)
237 {
238 #ifndef CONFIG_64BIT
239 asm volatile("lpsw %0" : : "Q" (psw) : "cc");
240 #else
241 asm volatile("lpswe %0" : : "Q" (psw) : "cc");
242 #endif
243 }
244
245 /*
246 * Set PSW mask to specified value, while leaving the
247 * PSW addr pointing to the next instruction.
248 */
__load_psw_mask(unsigned long mask)249 static inline void __load_psw_mask (unsigned long mask)
250 {
251 unsigned long addr;
252 psw_t psw;
253
254 psw.mask = mask;
255
256 #ifndef CONFIG_64BIT
257 asm volatile(
258 " basr %0,0\n"
259 "0: ahi %0,1f-0b\n"
260 " st %0,%O1+4(%R1)\n"
261 " lpsw %1\n"
262 "1:"
263 : "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc");
264 #else /* CONFIG_64BIT */
265 asm volatile(
266 " larl %0,1f\n"
267 " stg %0,%O1+8(%R1)\n"
268 " lpswe %1\n"
269 "1:"
270 : "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc");
271 #endif /* CONFIG_64BIT */
272 }
273
274 /*
275 * Rewind PSW instruction address by specified number of bytes.
276 */
__rewind_psw(psw_t psw,unsigned long ilc)277 static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc)
278 {
279 #ifndef CONFIG_64BIT
280 if (psw.addr & PSW_ADDR_AMODE)
281 /* 31 bit mode */
282 return (psw.addr - ilc) | PSW_ADDR_AMODE;
283 /* 24 bit mode */
284 return (psw.addr - ilc) & ((1UL << 24) - 1);
285 #else
286 unsigned long mask;
287
288 mask = (psw.mask & PSW_MASK_EA) ? -1UL :
289 (psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 :
290 (1UL << 24) - 1;
291 return (psw.addr - ilc) & mask;
292 #endif
293 }
294
295 /*
296 * Function to stop a processor until the next interrupt occurs
297 */
298 void enabled_wait(void);
299
300 /*
301 * Function to drop a processor into disabled wait state
302 */
disabled_wait(unsigned long code)303 static inline void __noreturn disabled_wait(unsigned long code)
304 {
305 unsigned long ctl_buf;
306 psw_t dw_psw;
307
308 dw_psw.mask = PSW_MASK_BASE | PSW_MASK_WAIT | PSW_MASK_BA | PSW_MASK_EA;
309 dw_psw.addr = code;
310 /*
311 * Store status and then load disabled wait psw,
312 * the processor is dead afterwards
313 */
314 #ifndef CONFIG_64BIT
315 asm volatile(
316 " stctl 0,0,0(%2)\n"
317 " ni 0(%2),0xef\n" /* switch off protection */
318 " lctl 0,0,0(%2)\n"
319 " stpt 0xd8\n" /* store timer */
320 " stckc 0xe0\n" /* store clock comparator */
321 " stpx 0x108\n" /* store prefix register */
322 " stam 0,15,0x120\n" /* store access registers */
323 " std 0,0x160\n" /* store f0 */
324 " std 2,0x168\n" /* store f2 */
325 " std 4,0x170\n" /* store f4 */
326 " std 6,0x178\n" /* store f6 */
327 " stm 0,15,0x180\n" /* store general registers */
328 " stctl 0,15,0x1c0\n" /* store control registers */
329 " oi 0x1c0,0x10\n" /* fake protection bit */
330 " lpsw 0(%1)"
331 : "=m" (ctl_buf)
332 : "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc");
333 #else /* CONFIG_64BIT */
334 asm volatile(
335 " stctg 0,0,0(%2)\n"
336 " ni 4(%2),0xef\n" /* switch off protection */
337 " lctlg 0,0,0(%2)\n"
338 " lghi 1,0x1000\n"
339 " stpt 0x328(1)\n" /* store timer */
340 " stckc 0x330(1)\n" /* store clock comparator */
341 " stpx 0x318(1)\n" /* store prefix register */
342 " stam 0,15,0x340(1)\n"/* store access registers */
343 " stfpc 0x31c(1)\n" /* store fpu control */
344 " std 0,0x200(1)\n" /* store f0 */
345 " std 1,0x208(1)\n" /* store f1 */
346 " std 2,0x210(1)\n" /* store f2 */
347 " std 3,0x218(1)\n" /* store f3 */
348 " std 4,0x220(1)\n" /* store f4 */
349 " std 5,0x228(1)\n" /* store f5 */
350 " std 6,0x230(1)\n" /* store f6 */
351 " std 7,0x238(1)\n" /* store f7 */
352 " std 8,0x240(1)\n" /* store f8 */
353 " std 9,0x248(1)\n" /* store f9 */
354 " std 10,0x250(1)\n" /* store f10 */
355 " std 11,0x258(1)\n" /* store f11 */
356 " std 12,0x260(1)\n" /* store f12 */
357 " std 13,0x268(1)\n" /* store f13 */
358 " std 14,0x270(1)\n" /* store f14 */
359 " std 15,0x278(1)\n" /* store f15 */
360 " stmg 0,15,0x280(1)\n"/* store general registers */
361 " stctg 0,15,0x380(1)\n"/* store control registers */
362 " oi 0x384(1),0x10\n"/* fake protection bit */
363 " lpswe 0(%1)"
364 : "=m" (ctl_buf)
365 : "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc", "0", "1");
366 #endif /* CONFIG_64BIT */
367 while (1);
368 }
369
370 /*
371 * Use to set psw mask except for the first byte which
372 * won't be changed by this function.
373 */
374 static inline void
__set_psw_mask(unsigned long mask)375 __set_psw_mask(unsigned long mask)
376 {
377 __load_psw_mask(mask | (arch_local_save_flags() & ~(-1UL >> 8)));
378 }
379
380 #define local_mcck_enable() \
381 __set_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT | PSW_MASK_MCHECK)
382 #define local_mcck_disable() \
383 __set_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT)
384
385 /*
386 * Basic Machine Check/Program Check Handler.
387 */
388
389 extern void s390_base_mcck_handler(void);
390 extern void s390_base_pgm_handler(void);
391 extern void s390_base_ext_handler(void);
392
393 extern void (*s390_base_mcck_handler_fn)(void);
394 extern void (*s390_base_pgm_handler_fn)(void);
395 extern void (*s390_base_ext_handler_fn)(void);
396
397 #define ARCH_LOW_ADDRESS_LIMIT 0x7fffffffUL
398
399 extern int memcpy_real(void *, void *, size_t);
400 extern void memcpy_absolute(void *, void *, size_t);
401
402 #define mem_assign_absolute(dest, val) { \
403 __typeof__(dest) __tmp = (val); \
404 \
405 BUILD_BUG_ON(sizeof(__tmp) != sizeof(val)); \
406 memcpy_absolute(&(dest), &__tmp, sizeof(__tmp)); \
407 }
408
409 /*
410 * Helper macro for exception table entries
411 */
412 #define EX_TABLE(_fault, _target) \
413 ".section __ex_table,\"a\"\n" \
414 ".align 4\n" \
415 ".long (" #_fault ") - .\n" \
416 ".long (" #_target ") - .\n" \
417 ".previous\n"
418
419 #else /* __ASSEMBLY__ */
420
421 #define EX_TABLE(_fault, _target) \
422 .section __ex_table,"a" ; \
423 .align 4 ; \
424 .long (_fault) - . ; \
425 .long (_target) - . ; \
426 .previous
427
428 #endif /* __ASSEMBLY__ */
429
430 #endif /* __ASM_S390_PROCESSOR_H */
431