Home
last modified time | relevance | path

Searched refs:__reg (Results 1 – 7 of 7) sorted by relevance

/arch/frv/include/asm/
Dirc-regs.h15 #define __reg(ADDR) (*(volatile unsigned long *)(ADDR)) macro
17 #define __get_TM0() ({ __reg(0xfeff9800); })
18 #define __get_TM1() ({ __reg(0xfeff9808); })
19 #define __set_TM1(V) do { __reg(0xfeff9808) = (V); mb(); } while(0)
24 unsigned long tm1 = __reg(0xfeff9808); \
27 __reg(0xfeff9808) = tm1; \
31 #define __get_RS(C) ({ (__reg(0xfeff9810) >> ((C)+16)) & 1; })
33 #define __clr_RC(C) do { __reg(0xfeff9818) = 1 << ((C)+16); mb(); } while(0)
35 #define __get_MASK(C) ({ (__reg(0xfeff9820) >> ((C)+16)) & 1; })
36 #define __set_MASK(C) do { __reg(0xfeff9820) |= 1 << ((C)+16); mb(); } while(0)
[all …]
Dgpio-regs.h15 #define __reg(ADDR) (*(volatile unsigned long *)(ADDR)) macro
17 #define __get_PDR() ({ __reg(0xfeff0400); })
18 #define __set_PDR(V) do { __reg(0xfeff0400) = (V); mb(); } while(0)
20 #define __get_GPDR() ({ __reg(0xfeff0408); })
21 #define __set_GPDR(V) do { __reg(0xfeff0408) = (V); mb(); } while(0)
23 #define __get_SIR() ({ __reg(0xfeff0410); })
24 #define __set_SIR(V) do { __reg(0xfeff0410) = (V); mb(); } while(0)
26 #define __get_SOR() ({ __reg(0xfeff0418); })
27 #define __set_SOR(V) do { __reg(0xfeff0418) = (V); mb(); } while(0)
29 #define __set_PDSR(V) do { __reg(0xfeff0420) = (V); mb(); } while(0)
[all …]
Dserial-regs.h22 #define __get_UART0(R) ({ __reg(UART0_BASE + (R) * 8) >> 24; })
23 #define __get_UART1(R) ({ __reg(UART1_BASE + (R) * 8) >> 24; })
24 #define __set_UART0(R,V) do { __reg(UART0_BASE + (R) * 8) = (V) << 24; } while(0)
25 #define __set_UART1(R,V) do { __reg(UART1_BASE + (R) * 8) = (V) << 24; } while(0)
/arch/ia64/include/asm/
Dparavirt_privop.h446 register unsigned long __reg asm ("r8") = (reg); \
452 : PARAVIRT_OP(getreg), "0"(__reg) \
462 register unsigned long __reg asm ("r9") = reg; \
472 "1"(__reg), "0"(__val) \
/arch/sparc/kernel/
Dprom_irqtrans.c83 #define sabre_read(__reg) \ argument
87 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
317 #define schizo_read(__reg) \ argument
321 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
325 #define schizo_write(__reg, __val) \ argument
328 : "r" (__val), "r" (__reg), \
Diommu.c33 #define iommu_read(__reg) \ argument
37 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
41 #define iommu_write(__reg, __val) \ argument
44 : "r" (__val), "r" (__reg), \
/arch/frv/kernel/
Dsetup.c785 __reg(UART0_BASE + UART_IER * 8) = 0; in setup_arch()
789 __reg(UART1_BASE + UART_IER * 8) = 0; in setup_arch()