| /arch/xtensa/lib/ |
| D | memcopy.S | 90 s8i a6, a5, 0
91 addi a5, a5, 1
110 s8i a6, a5, 0
111 addi a5, a5, 1
112 _bbci.l a5, 1, .Ldstaligned # if dst is now aligned, then
121 s8i a6, a5, 0
122 s8i a7, a5, 1
123 addi a5, a5, 2
133 mov a5, a2 # copy dst so that a2 is return value
156 s32i a6, a5, 0
[all …]
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| D | memset.S | 52 mov a5, a2 # copy dst so that a2 is return value
73 add a6, a6, a5 # a6 = end of last 16B chunk
76 EX(s32i, a3, a5, 0, memset_fixup)
77 EX(s32i, a3, a5, 4, memset_fixup)
78 EX(s32i, a3, a5, 8, memset_fixup)
79 EX(s32i, a3, a5, 12, memset_fixup)
80 addi a5, a5, 16
82 blt a5, a6, .Loop1
87 EX(s32i, a3, a5, 0, memset_fixup)
88 EX(s32i, a3, a5, 4, memset_fixup)
[all …]
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| D | checksum.S | 50 extui a5, a2, 0, 2
51 bnez a5, 8f /* branch if 2-byte aligned */
54 srli a5, a3, 5 /* 32-byte chunks */
56 loopgtz a5, 2f
58 beqz a5, 2f
59 slli a5, a5, 5
60 add a5, a5, a2 /* a5 = end of last 32-byte chunk */
81 blt a2, a5, .Loop1
84 extui a5, a3, 2, 3 /* remaining 4-byte chunks */
86 loopgtz a5, 3f
[all …]
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| D | usercopy.S | 82 mov a5, a2 # copy dst so that a2 is return value
107 EX(s8i, a6, a5, 0, s_fixup)
108 addi a5, a5, 1
110 bbci.l a5, 1, .Ldstaligned # if dst is now aligned, then
118 EX(s8i, a6, a5, 0, s_fixup)
119 EX(s8i, a7, a5, 1, s_fixup)
120 addi a5, a5, 2
140 EX(s8i, a6, a5, 0, s_fixup)
141 addi a5, a5, 1
166 EX(s32i, a6, a5, 0, s_fixup)
[all …]
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| D | strnlen_user.S | 44 # a5/ mask0
60 movi a5, MASK0 # mask for byte 0
82 bnone a9, a5, .Lz0 # if byte 0 is zero
96 bnone a9, a5, .Lz0 # if byte 0 is zero
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| D | strncpy_user.S | 47 # a5/ mask0
65 movi a5, MASK0 # mask for byte 0
122 bnone a9, a5, .Lz0 # if byte 0 is zero
141 bnone a9, a5, .Lz0 # if byte 0 is zero
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| /arch/xtensa/include/asm/ |
| D | initialize_mmu.h | 97 addi a5, a2, -6
98 add a4, a4, a5
105 add a5, a2, a4
106 3: idtlb a5
107 iitlb a5
108 add a5, a5, a4
109 bne a5, a2, 3b
117 movi a5, 0xd0000005
119 wdtlb a4, a5
120 witlb a4, a5
[all …]
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| /arch/xtensa/kernel/ |
| D | align.S | 169 s32i a5, a2, PT_AREG5
209 l32i a5, a3, 4
212 __src_b a4, a4, a5 # a4 has the instruction
216 extui a5, a4, INSN_OP0, 4 # get insn.op0 nibble
219 _beqi a5, OP0_L32I_N, .Lload # L32I.N, jump
220 addi a6, a5, -OP0_S32I_N
228 .Lstore:movi a5, .Lstore_table # table
230 addx8 a5, a6, a5
231 jx a5 # jump into table
241 l32e a5, a3, -8
[all …]
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| D | coprocessor.S | 63 xchal_cp##x##_store a2 a4 a5 a6 a7; \
80 xchal_cp##x##_load a2 a4 a5 a6 a7; \
261 s32i a5, a1, PT_AREG5
289 l32i a5, a4, THREAD_CPENABLE
290 xor a5, a5, a2 # (1 << cp-id) still in a2
291 s32i a5, a4, THREAD_CPENABLE
298 movi a5, .Lsave_cp_regs_jump_table
300 addx8 a3, a3, a5 # a3: coprocessor number
304 add a4, a3, a5 # a4: address of save routine
321 movi a5, .Lload_cp_regs_jump_table
[all …]
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| D | vectors.S | 667 s32e a0, a5, -16
668 s32e a1, a5, -12
669 s32e a2, a5, -8
670 s32e a3, a5, -4
698 l32e a0, a5, -16
699 l32e a1, a5, -12
700 l32e a2, a5, -8
701 l32e a3, a5, -4
716 s32e a5, a0, -28
733 l32e a5, a7, -28
[all …]
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| D | entry.S | 152 s32i a5, a1, PT_AREG5
200 s32i a0, a5, PT_AREG_END - 16
201 s32i a1, a5, PT_AREG_END - 12
202 s32i a2, a5, PT_AREG_END - 8
203 s32i a3, a5, PT_AREG_END - 4
205 addi a1, a5, -16
386 save_xtregs_opt a1 a2 a4 a5 a6 a7 PT_XTREGS_OPT
500 load_xtregs_opt a1 a2 a4 a5 a6 a7 PT_XTREGS_OPT
538 mov a3, a5
544 l32i a5, a3, PT_AREG_END + 4
[all …]
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| /arch/xtensa/boot/boot-redboot/ |
| D | bootstrap.S | 57 rsr a5, windowbase
58 ssl a5
82 movi a5, __start_a0
84 sub a0, a4, a5
87 movi a5, __reloc_end
91 # a5: compiled end address
107 blt a8, a5, 1b
114 ___flush_dcache_all a5 a6
118 ___invalidate_icache_all a5 a6
151 movi.n a5, 0
[all …]
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| /arch/mips/kernel/ |
| D | linux32.c | 111 unsigned long, unused, unsigned long, a4, unsigned long, a5)
113 return sys_pread64(fd, buf, count, merge_64(a4, a5));
117 size_t, count, u32, unused, u64, a4, u64, a5)
119 return sys_pwrite64(fd, buf, count, merge_64(a4, a5));
144 unsigned long a4, unsigned long a5, in sys32_sync_file_range() argument
148 merge_64(a2, a3), merge_64(a4, a5), in sys32_sync_file_range()
154 unsigned long a4, unsigned long a5, in sys32_fadvise64_64() argument
158 merge_64(a2, a3), merge_64(a4, a5), in sys32_fadvise64_64()
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| /arch/x86/platform/uv/ |
| D | bios_uv.c | 31 s64 uv_bios_call(enum uv_bios_cmd which, u64 a1, u64 a2, u64 a3, u64 a4, u64 a5) in uv_bios_call() argument
43 a1, a2, a3, a4, a5); in uv_bios_call()
49 u64 a4, u64 a5) in uv_bios_call_irqsave() argument
55 ret = uv_bios_call(which, a1, a2, a3, a4, a5); in uv_bios_call_irqsave()
62 u64 a4, u64 a5) in uv_bios_call_reentrant() argument
67 ret = uv_bios_call(which, a1, a2, a3, a4, a5); in uv_bios_call_reentrant()
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| /arch/arm/boot/dts/ |
| D | vexpress-v2p-ca5s.dts | 38 compatible = "arm,cortex-a5";
45 compatible = "arm,cortex-a5";
81 compatible = "arm,cortex-a5-scu";
86 compatible = "arm,cortex-a5-twd-timer";
92 compatible = "arm,cortex-a5-global-timer",
100 compatible = "arm,cortex-a5-twd-wdt";
106 compatible = "arm,cortex-a5-gic", "arm,cortex-a9-gic";
122 compatible = "arm,cortex-a5-pmu";
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| /arch/m68k/lib/ |
| D | mulsi3.S | 85 #define a5 REG (a5) macro
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| D | modsi3.S | 85 #define a5 REG (a5) macro
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| D | umodsi3.S | 85 #define a5 REG (a5) macro
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| D | divsi3.S | 85 #define a5 REG (a5) macro
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| /arch/m68k/include/asm/ |
| D | a.out-core.h | 54 dump->regs.a5 = sw->a5; in aout_dump_thread()
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| D | user.h | 41 long a0,a1,a2,a3,a4,a5,a6; member
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| /arch/alpha/include/uapi/asm/ |
| D | regdef.h | 29 #define a5 $21 macro
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| /arch/x86/include/asm/xen/ |
| D | hypercall.h | 131 #define __HYPERCALL_5ARG(a1,a2,a3,a4,a5) \ argument
132 __HYPERCALL_4ARG(a1,a2,a3,a4) __arg5 = (unsigned long)(a5);
196 #define _hypercall5(type, name, a1, a2, a3, a4, a5) \ argument
199 __HYPERCALL_5ARG(a1, a2, a3, a4, a5); \
211 unsigned long a5) in privcmd_call() argument
214 __HYPERCALL_5ARG(a1, a2, a3, a4, a5); in privcmd_call()
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| /arch/m68k/include/uapi/asm/ |
| D | ptrace.h | 63 unsigned long a5; member
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| /arch/arm/include/asm/xen/ |
| D | hypercall.h | 41 unsigned long a4, unsigned long a5);
|