Searched refs:accesses (Results 1 – 25 of 25) sorted by relevance
| /arch/mips/kvm/ |
| D | Kconfig | 37 bool "Maintain counters for COP0 accesses"
40 Maintain statistics for Guest COP0 accesses.
41 A histogram of COP0 accesses is printed when the VM is
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| /arch/cris/include/arch-v32/mach-fs/mach/ |
| D | arbiter.h | 24 unsigned long clients, unsigned long accesses,
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| /arch/cris/include/arch-v32/mach-a3/mach/ |
| D | arbiter.h | 30 unsigned long clients, unsigned long accesses,
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| /arch/metag/ |
| D | Kconfig.soc | 49 All memory accesses will be checked for alignment and an exception
50 raised on unaligned accesses. This feature does cost performance
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| /arch/ |
| D | Kconfig | 105 Some architectures require 64 bit accesses to be 64 bit
108 architectures which can do 64 bit accesses, as well as 64 bit
112 accesses are required to be 64 bit aligned in this way even
116 information on the topic of unaligned memory accesses.
121 Some architectures are unable to perform unaligned accesses
123 unable to perform such accesses efficiently (e.g. trap on
128 perform unaligned accesses efficiently to allow different
135 information on the topic of unaligned memory accesses.
445 some 32-bit arches may require multiple accesses, so proper
446 locking is needed to protect against concurrent accesses.
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| /arch/cris/arch-v32/mach-fs/ |
| D | arbiter.c | 264 unsigned long clients, unsigned long accesses, in crisv32_arbiter_watch() argument
294 accesses); in crisv32_arbiter_watch()
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| /arch/cris/arch-v32/mach-a3/ |
| D | arbiter.c | 363 unsigned long clients, unsigned long accesses, in crisv32_arbiter_watch() argument
417 rw_op, accesses); in crisv32_arbiter_watch()
433 rw_op, accesses); in crisv32_arbiter_watch()
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| /arch/arm/kvm/ |
| D | init.S | 95 @ Use the same memory attributes for hyp. accesses as the kernel
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| D | interrupts_head.S | 614 bic r3, r2, r3 @ Don't trap defined coproc-accesses
636 orr r2, r2, r3 @ Trap some perfmon accesses
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| /arch/mips/cavium-octeon/ |
| D | Kconfig | 18 CVMSEG LM is a segment that accesses portions of the dcache as a
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| /arch/arm/mach-pxa/ |
| D | sleep.S | 159 @ external accesses after SDRAM is put in self-refresh mode
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| /arch/arm/mm/ |
| D | cache-v7.S | 91 dmb @ ensure ordering with previous memory accesses
120 dmb @ ensure ordering with previous memory accesses
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| D | Kconfig | 937 PL310 can handle normal accesses while it is in progress. Under very
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| /arch/frv/ |
| D | Kconfig | 292 generate accesses to the data using GR16-relative addressing which
300 So if the linker starts complaining that accesses to GPREL data are
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| /arch/mn10300/ |
| D | Kconfig.debug | 20 accesses to make sure the misalignment handler deals them with
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| /arch/blackfin/mach-bf548/ |
| D | Kconfig | 32 bool "DMA has priority over core for ext. accesses"
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| /arch/m68k/ |
| D | Kconfig.cpu | 365 bool "Use write-through caching for 68060 supervisor accesses"
371 here will force supervisor (kernel) accesses to use writethrough
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| /arch/xtensa/ |
| D | Kconfig | 145 memory accesses in hardware but through an exception handler.
146 Per default, unaligned memory accesses are disabled in user space.
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| /arch/arm/mach-ixp4xx/ |
| D | Kconfig | 216 is that every PCI access requires three local register accesses
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| /arch/x86/math-emu/ |
| D | README | 87 variables. The code which accesses user memory is confined to five
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| /arch/arm64/ |
| D | Kconfig | 333 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
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| /arch/x86/ |
| D | Kconfig | 367 and accesses the local apic via MSRs not via mmio.
520 MSR's for some register accesses, mostly but not limited to thermal
1133 MSR accesses are directed to a specific CPU on multi-processor
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| /arch/arm/ |
| D | Kconfig | 1107 the L1 caching of the NEON accesses and disables the PLD instruction
1714 Increase kernel security by ensuring that normal kernel accesses
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| D | Kconfig.debug | 1256 bool "Use 32-bit accesses for 8250 UART"
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| /arch/blackfin/ |
| D | Kconfig | 1133 bool "DMA has priority over core for ext. accesses"
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