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Searched refs:bridge_base (Results 1 – 6 of 6) sorted by relevance

/arch/powerpc/boot/
Dcuboot-c2k.c26 static u8 *bridge_base; variable
53 mv64x60_config_ctlr_windows(bridge_base, bridge_pbase, is_coherent); in c2k_bridge_setup()
58 enables = in_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE)); in c2k_bridge_setup()
60 out_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE), enables); in c2k_bridge_setup()
77 mv64x60_config_pci_windows(bridge_base, bridge_pbase, bus, 0, in c2k_bridge_setup()
111 mv64x60_config_cpu2pci_window(bridge_base, bus, in c2k_bridge_setup()
117 out_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE), in c2k_bridge_setup()
126 mem_size = mv64x60_get_mem_size(bridge_base); in c2k_fixups()
142 if (bridge_base != 0) { in c2k_reset()
143 temp = in_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_0)); in c2k_reset()
[all …]
Dmv64x60.c181 u32 mv64x60_cfg_read(u8 *bridge_base, u8 hose, u8 bus, u8 devfn, u8 offset) in mv64x60_cfg_read() argument
183 out_le32((u32 *)(bridge_base + mv64x60_pci_cfgio[hose].addr), in mv64x60_cfg_read()
185 return in_le32((u32 *)(bridge_base + mv64x60_pci_cfgio[hose].data)); in mv64x60_cfg_read()
188 void mv64x60_cfg_write(u8 *bridge_base, u8 hose, u8 bus, u8 devfn, u8 offset, in mv64x60_cfg_write() argument
191 out_le32((u32 *)(bridge_base + mv64x60_pci_cfgio[hose].addr), in mv64x60_cfg_write()
193 out_le32((u32 *)(bridge_base + mv64x60_pci_cfgio[hose].data), val); in mv64x60_cfg_write()
280 void mv64x60_config_ctlr_windows(u8 *bridge_base, u8 *bridge_pbase, in mv64x60_config_ctlr_windows() argument
286 out_le32((u32 *)(bridge_base + MV64x60_ENET2MEM_BAR_ENABLE), 0x3f); in mv64x60_config_ctlr_windows()
287 out_le32((u32 *)(bridge_base + MV64x60_MPSC2MEM_BAR_ENABLE), 0xf); in mv64x60_config_ctlr_windows()
288 out_le32((u32 *)(bridge_base + MV64x60_ENET2MEM_BAR_ENABLE), 0xff); in mv64x60_config_ctlr_windows()
[all …]
Dprpmc2800.c38 static u8 *bridge_base; variable
342 mv64x60_config_ctlr_windows(bridge_base, bridge_pbase, is_coherent); in prpmc2800_bridge_setup()
343 mv64x60_config_pci_windows(bridge_base, bridge_pbase, 0, 0, mem_size, in prpmc2800_bridge_setup()
362 enables = in_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE)); in prpmc2800_bridge_setup()
364 out_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE), enables); in prpmc2800_bridge_setup()
390 mv64x60_config_cpu2pci_window(bridge_base, 0, pci_base_hi, in prpmc2800_bridge_setup()
395 out_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE), enables); in prpmc2800_bridge_setup()
408 mem_size = (bip) ? bip->mem_size : mv64x60_get_mem_size(bridge_base); in prpmc2800_fixups()
478 if (bridge_base != 0) { in prpmc2800_reset()
479 temp = in_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_0)); in prpmc2800_reset()
[all …]
Dmv64x60.h48 u32 mv64x60_cfg_read(u8 *bridge_base, u8 hose, u8 bus, u8 devfn,
50 void mv64x60_cfg_write(u8 *bridge_base, u8 hose, u8 bus, u8 devfn,
53 void mv64x60_config_ctlr_windows(u8 *bridge_base, u8 *bridge_pbase,
55 void mv64x60_config_pci_windows(u8 *bridge_base, u8 *bridge_pbase, u8 hose,
57 void mv64x60_config_cpu2pci_window(u8 *bridge_base, u8 hose, u32 pci_base_hi,
60 u32 mv64x60_get_mem_size(u8 *bridge_base);
/arch/arm/plat-orion/
Dtime.c48 static void __iomem *bridge_base; variable
86 writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF); in orion_clkevt_next_event()
88 u = readl(bridge_base + BRIDGE_MASK_OFF); in orion_clkevt_next_event()
90 writel(u, bridge_base + BRIDGE_MASK_OFF); in orion_clkevt_next_event()
126 u = readl(bridge_base + BRIDGE_MASK_OFF); in orion_clkevt_mode()
127 writel(u | BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF); in orion_clkevt_mode()
145 u = readl(bridge_base + BRIDGE_MASK_OFF); in orion_clkevt_mode()
146 writel(u & ~BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF); in orion_clkevt_mode()
151 writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF); in orion_clkevt_mode()
170 writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF); in orion_timer_interrupt()
[all …]
/arch/arm/plat-orion/include/plat/
Dtime.h16 void orion_time_init(void __iomem *bridge_base, u32 bridge_timer1_clr_mask,