Searched refs:ccm_base (Results 1 – 6 of 6) sorted by relevance
17 #define CCM_CCR (ccm_base + 0x00)18 #define CCM_CSR (ccm_base + 0x04)19 #define CCM_CCSR (ccm_base + 0x08)20 #define CCM_CACRR (ccm_base + 0x0c)21 #define CCM_CSCMR1 (ccm_base + 0x10)22 #define CCM_CSCDR1 (ccm_base + 0x14)23 #define CCM_CSCDR2 (ccm_base + 0x18)24 #define CCM_CSCDR3 (ccm_base + 0x1c)25 #define CCM_CSCMR2 (ccm_base + 0x20)26 #define CCM_CSCDR4 (ccm_base + 0x24)[all …]
34 #define MXC_CCM_CCR (ccm_base + 0x00)35 #define MXC_CCM_CCDR (ccm_base + 0x04)36 #define MXC_CCM_CSR (ccm_base + 0x08)37 #define MXC_CCM_CCSR (ccm_base + 0x0c)38 #define MXC_CCM_CACRR (ccm_base + 0x10)39 #define MXC_CCM_CBCDR (ccm_base + 0x14)40 #define MXC_CCM_CBCMR (ccm_base + 0x18)41 #define MXC_CCM_CSCMR1 (ccm_base + 0x1c)42 #define MXC_CCM_CSCMR2 (ccm_base + 0x20)43 #define MXC_CCM_CSCDR1 (ccm_base + 0x24)[all …]
67 static void __iomem *ccm_base; variable195 struct imx6_pm_base ccm_base; member204 u32 val = readl_relaxed(ccm_base + CGPR); in imx6q_set_int_mem_clk_lpm()209 writel_relaxed(val, ccm_base + CGPR); in imx6q_set_int_mem_clk_lpm()223 val = readl_relaxed(ccm_base + CCR); in imx6q_enable_rbc()226 writel_relaxed(val, ccm_base + CCR); in imx6q_enable_rbc()229 val = readl_relaxed(ccm_base + CCR); in imx6q_enable_rbc()232 writel(val, ccm_base + CCR); in imx6q_enable_rbc()250 val = readl_relaxed(ccm_base + CLPCR); in imx6q_enable_wb()253 writel_relaxed(val, ccm_base + CLPCR); in imx6q_enable_wb()[all …]
67 static void __iomem *ccm_base; variable73 ccm_base = base; in imx5_pm_set_ccm_base()89 ccm_clpcr = __raw_readl(ccm_base + MXC_CCM_CLPCR) & in mx5_cpu_lp_set()131 __raw_writel(ccm_clpcr, ccm_base + MXC_CCM_CLPCR); in mx5_cpu_lp_set()213 WARN_ON(!ccm_base || !cortex_base || !gpc_base); in imx5_pm_common_init()
104 static void __iomem *ccm_base; variable135 if (readl_relaxed(ccm_base + CCSR) & BM_CCSR_PLL1_SW_CLK_SEL) { in imx6sl_get_arm_divider_for_wait()176 saved_arm_div = readl_relaxed(ccm_base + CACRR); in imx6sl_set_wait_clk()177 writel_relaxed(arm_div_for_wait, ccm_base + CACRR); in imx6sl_set_wait_clk()179 writel_relaxed(saved_arm_div, ccm_base + CACRR); in imx6sl_set_wait_clk()181 while (__raw_readl(ccm_base + CDHIPR) & BM_CDHIPR_ARM_PODF_BUSY) in imx6sl_set_wait_clk()289 ccm_base = base; in imx6sl_clocks_init()
57 #define ccm(x) (ccm_base + (x))93 void __iomem *ccm_base) in __mx25_clocks_init() argument95 BUG_ON(!ccm_base); in __mx25_clocks_init()