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Searched refs:csr (Results 1 – 25 of 47) sorted by relevance

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/arch/alpha/kernel/
Dcore_tsunami.c180 volatile unsigned long *csr; in tsunami_pci_tbi() local
185 csr = &pchip->tlbia.csr; in tsunami_pci_tbi()
187 csr = &pchip->tlbiv.csr; in tsunami_pci_tbi()
193 *csr = value; in tsunami_pci_tbi()
195 *csr; in tsunami_pci_tbi()
226 TSUNAMI_cchip->misc.csr |= (1L << 28); /* clear NXM... */ in tsunami_probe_write()
230 if (TSUNAMI_cchip->misc.csr & (1L << 28)) { in tsunami_probe_write()
231 int source = (TSUNAMI_cchip->misc.csr >> 29) & 7; in tsunami_probe_write()
232 TSUNAMI_cchip->misc.csr |= (1L << 28); /* ...and unlock NXS. */ in tsunami_probe_write()
250 if (tsunami_probe_read(&pchip->pctl.csr) == 0) in tsunami_init_one_pchip()
[all …]
Dcore_wildfire.c118 pci->pci_window[0].wbase.csr = hose->sg_isa->dma_base | 3; in wildfire_init_hose()
119 pci->pci_window[0].wmask.csr = (hose->sg_isa->size - 1) & 0xfff00000; in wildfire_init_hose()
120 pci->pci_window[0].tbase.csr = virt_to_phys(hose->sg_isa->ptes); in wildfire_init_hose()
122 pci->pci_window[1].wbase.csr = 0x40000000 | 1; in wildfire_init_hose()
123 pci->pci_window[1].wmask.csr = (0x40000000 -1) & 0xfff00000; in wildfire_init_hose()
124 pci->pci_window[1].tbase.csr = 0; in wildfire_init_hose()
126 pci->pci_window[2].wbase.csr = 0x80000000 | 1; in wildfire_init_hose()
127 pci->pci_window[2].wmask.csr = (0x40000000 -1) & 0xfff00000; in wildfire_init_hose()
128 pci->pci_window[2].tbase.csr = 0x40000000; in wildfire_init_hose()
130 pci->pci_window[3].wbase.csr = hose->sg_pci->dma_base | 3; in wildfire_init_hose()
[all …]
Dcore_titan.c207 volatile unsigned long *csr; in titan_pci_tbi() local
220 csr = &port->port_specific.g.gtlbia.csr; in titan_pci_tbi()
222 csr = &port->port_specific.g.gtlbiv.csr; in titan_pci_tbi()
229 *csr = value; in titan_pci_tbi()
231 *csr; in titan_pci_tbi()
240 pctl.pctl_q_whole = port->pctl.csr; in titan_query_agp()
293 saved_config[index].wsba[0] = port->wsba[0].csr; in titan_init_one_pachip_port()
294 saved_config[index].wsm[0] = port->wsm[0].csr; in titan_init_one_pachip_port()
295 saved_config[index].tba[0] = port->tba[0].csr; in titan_init_one_pachip_port()
297 saved_config[index].wsba[1] = port->wsba[1].csr; in titan_init_one_pachip_port()
[all …]
Dsys_marvel.c96 ctl = &io7->csrs->PO7_LSI_CTL[irq & 0xff].csr; /* assume LSI */ in io7_get_irq_ctl()
98 ctl = &io7->csrs->PO7_MSI_CTL[((irq - 0x80) >> 5) & 0x0f].csr; in io7_get_irq_ctl()
174 volatile unsigned long *csr, in io7_redirect_irq() argument
179 val = *csr; in io7_redirect_irq()
183 *csr = val; in io7_redirect_irq()
185 *csr; in io7_redirect_irq()
196 val = io7->csrs->PO7_LSI_CTL[which].csr; in io7_redirect_one_lsi()
200 io7->csrs->PO7_LSI_CTL[which].csr = val; in io7_redirect_one_lsi()
202 io7->csrs->PO7_LSI_CTL[which].csr; in io7_redirect_one_lsi()
213 val = io7->csrs->PO7_MSI_CTL[which].csr; in io7_redirect_one_msi()
[all …]
Derr_marvel.c817 err_sum |= io7->csrs->PO7_ERROR_SUM.csr; in marvel_find_io7_with_error()
821 err_sum |= io7->ports[i].csrs->POx_ERR_SUM.csr; in marvel_find_io7_with_error()
842 io->io_asic_rev = io7->csrs->IO_ASIC_REV.csr; in marvel_find_io7_with_error()
843 io->io_sys_rev = io7->csrs->IO_SYS_REV.csr; in marvel_find_io7_with_error()
844 io->io7_uph = io7->csrs->IO7_UPH.csr; in marvel_find_io7_with_error()
845 io->hpi_ctl = io7->csrs->HPI_CTL.csr; in marvel_find_io7_with_error()
846 io->crd_ctl = io7->csrs->CRD_CTL.csr; in marvel_find_io7_with_error()
847 io->hei_ctl = io7->csrs->HEI_CTL.csr; in marvel_find_io7_with_error()
848 io->po7_error_sum = io7->csrs->PO7_ERROR_SUM.csr; in marvel_find_io7_with_error()
849 io->po7_uncrr_sym = io7->csrs->PO7_UNCRR_SYM.csr; in marvel_find_io7_with_error()
[all …]
Dcore_marvel.c62 q = ev7csr->csr; in read_ev7_csr()
74 ev7csr->csr = q; in write_ev7_csr()
179 csrs->POx_ERR_SUM.csr = -1UL; in io7_clear_errors()
180 csrs->POx_TLB_ERR.csr = -1UL; in io7_clear_errors()
181 csrs->POx_SPL_COMPLT.csr = -1UL; in io7_clear_errors()
182 csrs->POx_TRANS_SUM.csr = -1UL; in io7_clear_errors()
190 p7csrs->PO7_ERROR_SUM.csr = -1UL; in io7_clear_errors()
191 p7csrs->PO7_UNCRR_SYM.csr = -1UL; in io7_clear_errors()
192 p7csrs->PO7_CRRCT_SYM.csr = -1UL; in io7_clear_errors()
263 io7_port->saved_wbase[i] = csrs->POx_WBASE[i].csr; in io7_init_hose()
[all …]
Dsys_titan.c83 dim0 = &cchip->dim0.csr; in titan_update_irq_hw()
84 dim1 = &cchip->dim1.csr; in titan_update_irq_hw()
85 dim2 = &cchip->dim2.csr; in titan_update_irq_hw()
86 dim3 = &cchip->dim3.csr; in titan_update_irq_hw()
103 dimB = &cchip->dim0.csr; in titan_update_irq_hw()
104 if (bcpu == 1) dimB = &cchip->dim1.csr; in titan_update_irq_hw()
105 else if (bcpu == 2) dimB = &cchip->dim2.csr; in titan_update_irq_hw()
106 else if (bcpu == 3) dimB = &cchip->dim3.csr; in titan_update_irq_hw()
Dsys_dp264.c68 dim0 = &cchip->dim0.csr; in tsunami_update_irq_hw()
69 dim1 = &cchip->dim1.csr; in tsunami_update_irq_hw()
70 dim2 = &cchip->dim2.csr; in tsunami_update_irq_hw()
71 dim3 = &cchip->dim3.csr; in tsunami_update_irq_hw()
88 if (bcpu == 0) dimB = &cchip->dim0.csr; in tsunami_update_irq_hw()
89 else if (bcpu == 1) dimB = &cchip->dim1.csr; in tsunami_update_irq_hw()
90 else if (bcpu == 2) dimB = &cchip->dim2.csr; in tsunami_update_irq_hw()
91 else dimB = &cchip->dim3.csr; in tsunami_update_irq_hw()
197 pld = TSUNAMI_cchip->dir0.csr; in dp264_device_interrupt()
/arch/sparc/kernel/
Debus.c73 u32 csr = 0; in ebus_dma_irq() local
76 csr = readl(p->regs + EBDMA_CSR); in ebus_dma_irq()
77 writel(csr, p->regs + EBDMA_CSR); in ebus_dma_irq()
80 if (csr & EBDMA_CSR_ERR_PEND) { in ebus_dma_irq()
84 } else if (csr & EBDMA_CSR_INT_PEND) { in ebus_dma_irq()
86 (csr & EBDMA_CSR_TC) ? in ebus_dma_irq()
98 u32 csr; in ebus_dma_register() local
112 csr = EBDMA_CSR_BURST_SZ_16 | EBDMA_CSR_EN_CNT; in ebus_dma_register()
115 csr |= EBDMA_CSR_TCI_DIS; in ebus_dma_register()
117 writel(csr, p->regs + EBDMA_CSR); in ebus_dma_register()
[all …]
/arch/sh/kernel/cpu/
Dadc.c15 unsigned char csr; in adc_single() local
21 csr = __raw_readb(ADCSR); in adc_single()
22 csr = channel | ADCSR_ADST | ADCSR_CKS; in adc_single()
23 __raw_writeb(csr, ADCSR); in adc_single()
26 csr = __raw_readb(ADCSR); in adc_single()
27 } while ((csr & ADCSR_ADF) == 0); in adc_single()
29 csr &= ~(ADCSR_ADF | ADCSR_ADST); in adc_single()
30 __raw_writeb(csr, ADCSR); in adc_single()
/arch/mips/dec/
Dkn02-irq.c34 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + in unmask_kn02_irq() local
38 *csr = cached_kn02_csr; in unmask_kn02_irq()
43 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + in mask_kn02_irq() local
47 *csr = cached_kn02_csr; in mask_kn02_irq()
66 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + in init_kn02_irqs() local
72 *csr = cached_kn02_csr; in init_kn02_irqs()
Dkn01-berr.c53 volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR); in dec_kn01_be_ack() local
58 *csr = cached_kn01_csr | KN01_CSR_MEMERR; /* Clear bus IRQ. */ in dec_kn01_be_ack()
154 volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR); in dec_kn01_be_interrupt() local
158 if (!(*csr & KN01_CSR_MEMERR)) in dec_kn01_be_interrupt()
181 volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR); in dec_kn01_be_init() local
187 cached_kn01_csr = *csr; in dec_kn01_be_init()
193 *csr = cached_kn01_csr; in dec_kn01_be_init()
Decc-berr.c231 volatile u32 *csr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR); in dec_kn02_be_init() local
237 cached_kn02_csr = *csr | KN02_CSR_LEDS; in dec_kn02_be_init()
243 *csr = cached_kn02_csr; in dec_kn02_be_init()
/arch/mips/cavium-octeon/executive/
Dcvmx-interrupt-rsl.c53 union cvmx_asxx_int_en csr; in __cvmx_interrupt_asxx_enable() local
65 csr.u64 = cvmx_read_csr(CVMX_ASXX_INT_EN(block)); in __cvmx_interrupt_asxx_enable()
66 csr.s.txpsh = mask; in __cvmx_interrupt_asxx_enable()
67 csr.s.txpop = mask; in __cvmx_interrupt_asxx_enable()
68 csr.s.ovrflw = mask; in __cvmx_interrupt_asxx_enable()
69 cvmx_write_csr(CVMX_ASXX_INT_EN(block), csr.u64); in __cvmx_interrupt_asxx_enable()
/arch/sh/boards/mach-hp6xx/
Dpm.c42 u8 stbcr, csr; in pm_enter() local
49 csr = sh_wdt_read_csr(); in pm_enter()
50 csr &= ~WTCSR_TME; in pm_enter()
51 csr |= WTCSR_CKS_4096; in pm_enter()
52 sh_wdt_write_csr(csr); in pm_enter()
53 csr = sh_wdt_read_csr(); in pm_enter()
/arch/arm64/boot/dts/
Dapm-storm.dtsi153 reg-names = "csr-reg";
175 reg-names = "csr-reg";
184 reg-names = "csr-reg";
185 csr-mask = <0x3>;
194 reg-names = "csr-reg";
195 csr-mask = <0x3>;
204 reg-names = "csr-reg";
207 csr-offset = <0x4>;
208 csr-mask = <0x00>;
218 reg-names = "csr-reg";
[all …]
/arch/mips/kernel/
Dsignal.c72 uint32_t __user *csr = sc + abi->off_sc_fpc_csr; in copy_fp_to_sigcontext() local
81 err |= __put_user(current->thread.fpu.fcr31, csr); in copy_fp_to_sigcontext()
90 uint32_t __user *csr = sc + abi->off_sc_fpc_csr; in copy_fp_from_sigcontext() local
99 err |= __get_user(current->thread.fpu.fcr31, csr); in copy_fp_from_sigcontext()
111 uint32_t __user *csr = sc + abi->off_sc_fpc_csr; in save_hw_fp_context() local
113 return _save_fp_context(fpregs, csr); in save_hw_fp_context()
120 uint32_t __user *csr = sc + abi->off_sc_fpc_csr; in restore_hw_fp_context() local
122 return _restore_fp_context(fpregs, csr); in restore_hw_fp_context()
167 err = __put_user(read_msa_csr(), &msa->csr); in save_msa_extcontext()
174 err = __put_user(current->thread.fpu.msacsr, &msa->csr); in save_msa_extcontext()
[all …]
Dirq_txx9.c34 u32 csr; member
186 u32 csr = __raw_readl(&txx9_ircptr->csr); in txx9_irq() local
188 if (likely(!(csr & TXx9_IRCSR_IF))) in txx9_irq()
189 return TXX9_IRQ_BASE + (csr & (TXx9_MAX_IR - 1)); in txx9_irq()
Dsignal-common.h36 _save_fp_context(void __user *fpregs, void __user *csr);
38 _restore_fp_context(void __user *fpregs, void __user *csr);
/arch/m68k/sun3x/
Dtime.c48 h->csr |= C_WRITE; in sun3x_hwclk()
56 h->csr &= ~C_WRITE; in sun3x_hwclk()
58 h->csr |= C_READ; in sun3x_hwclk()
66 h->csr &= ~C_READ; in sun3x_hwclk()
Dtime.h9 volatile unsigned char csr; member
/arch/mips/include/asm/sibyte/
Dsb1250_defs.h255 #define SBWRITECSR(csr, val) *((volatile uint64_t *) PHYS_TO_K1(csr)) = (val) argument
256 #define SBREADCSR(csr) (*((volatile uint64_t *) PHYS_TO_K1(csr))) argument
/arch/powerpc/boot/
Dugecon.c48 u32 csr, data, cr; in ug_io_transaction() local
51 csr = EXI_CSR_CLK_32MHZ | EXI_CSR_CS_0; in ug_io_transaction()
52 out_be32(csr_reg, csr); in ug_io_transaction()
/arch/powerpc/platforms/embedded6xx/
Dusbgecko_udbg.c55 u32 csr, data, cr; in ug_io_transaction() local
58 csr = EXI_CSR_CLK_32MHZ | EXI_CSR_CS_0; in ug_io_transaction()
59 out_be32(csr_reg, csr); in ug_io_transaction()
/arch/mips/include/uapi/asm/
Ducontext.h39 unsigned int csr; member

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