| /arch/microblaze/lib/ |
| D | divsi3.S | 37 blti r5, div2 /* this traps r5 == 0x80000000 */
42 div2: label
55 bri div2 /* div2 */
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| D | udivsi3.S | 51 blti r5, div2
56 div2: label
69 bri div2 /* div2 */
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| D | umodsi3.S | 53 blti r5, div2
58 div2: label
71 bri div2 /* div2 */
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| D | modsi3.S | 42 div2: label
55 bri div2 /* div2 */
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| /arch/powerpc/boot/dts/fsl/ |
| D | p4080si-post.dtsi | 374 clock-output-names = "pll0", "pll0-div2";
382 clock-output-names = "pll1", "pll1-div2";
390 clock-output-names = "pll2", "pll2-div2";
398 clock-output-names = "pll3", "pll3-div2";
406 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
415 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
424 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
433 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
442 clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
451 clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
[all …]
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| D | t4240si-post.dtsi | 389 clock-output-names = "pll0", "pll0-div2", "pll0-div4";
397 clock-output-names = "pll1", "pll1-div2", "pll1-div4";
405 clock-output-names = "pll2", "pll2-div2", "pll2-div4";
413 clock-output-names = "pll3", "pll3-div2", "pll3-div4";
421 clock-output-names = "pll4", "pll4-div2", "pll4-div4";
431 clock-names = "pll0", "pll0-div2", "pll0-div4",
432 "pll1", "pll1-div2", "pll1-div4",
433 "pll2", "pll2-div2", "pll2-div4";
444 clock-names = "pll0", "pll0-div2", "pll0-div4",
445 "pll1", "pll1-div2", "pll1-div4",
[all …]
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| D | p5040si-post.dtsi | 319 clock-output-names = "pll0", "pll0-div2";
327 clock-output-names = "pll1", "pll1-div2";
335 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
344 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
353 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
362 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
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| D | p2041si-post.dtsi | 327 clock-output-names = "pll0", "pll0-div2";
335 clock-output-names = "pll1", "pll1-div2";
343 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
352 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
361 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
370 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
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| D | p3041si-post.dtsi | 354 clock-output-names = "pll0", "pll0-div2";
362 clock-output-names = "pll1", "pll1-div2";
370 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
379 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
388 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
397 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
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| D | b4420si-post.dtsi | 100 clock-output-names = "pll0", "pll0-div2", "pll0-div4";
108 clock-output-names = "pll1", "pll1-div2", "pll1-div4";
117 clock-names = "pll0", "pll0-div2", "pll0-div4",
118 "pll1", "pll1-div2", "pll1-div4";
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| D | t1040si-post.dtsi | 303 clock-output-names = "pll0", "pll0-div2", "pll0-div4";
311 clock-output-names = "pll1", "pll1-div2", "pll1-div4";
320 clock-names = "pll0", "pll0-div2", "pll1-div4",
321 "pll1", "pll1-div2", "pll1-div4";
331 clock-names = "pll0", "pll0-div2", "pll1-div4",
332 "pll1", "pll1-div2", "pll1-div4";
342 clock-names = "pll0", "pll0-div2", "pll1-div4",
343 "pll1", "pll1-div2", "pll1-div4";
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| D | b4860si-post.dtsi | 144 clock-output-names = "pll0", "pll0-div2", "pll0-div4";
152 clock-output-names = "pll1", "pll1-div2", "pll1-div4";
161 clock-names = "pll0", "pll0-div2", "pll0-div4",
162 "pll1", "pll1-div2", "pll1-div4";
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| D | p5020si-post.dtsi | 359 clock-output-names = "pll0", "pll0-div2";
367 clock-output-names = "pll1", "pll1-div2";
375 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
384 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
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| D | t2081si-post.dtsi | 326 clock-output-names = "pll0", "pll0-div2", "pll0-div4";
334 clock-output-names = "pll1", "pll1-div2", "pll1-div4";
343 clock-names = "pll0", "pll0-div2", "pll1-div4",
344 "pll1", "pll1-div2", "pll1-div4";
354 clock-names = "pll0", "pll0-div2", "pll1-div4",
355 "pll1", "pll1-div2", "pll1-div4";
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| /arch/sh/kernel/cpu/sh2a/ |
| D | clock-sh7264.c | 66 static int div2[] = { 1, 2, 3, 4, 6, 8, 12 }; variable
69 .divisors = div2,
70 .nr_divisors = ARRAY_SIZE(div2),
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| D | clock-sh7269.c | 94 static int div2[] = { 1, 2, 0, 4 }; variable
97 .divisors = div2,
98 .nr_divisors = ARRAY_SIZE(div2),
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| /arch/sh/kernel/cpu/sh4a/ |
| D | clock-sh7757.c | 51 static unsigned int div2[] = { 1, 1, 2, 1, 1, 4, 1, 6, variable
55 .divisors = div2,
56 .nr_divisors = ARRAY_SIZE(div2),
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| D | clock-shx3.c | 50 static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18, variable
54 .divisors = div2,
55 .nr_divisors = ARRAY_SIZE(div2),
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| D | clock-sh7785.c | 54 static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18, variable
58 .divisors = div2,
59 .nr_divisors = ARRAY_SIZE(div2),
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| D | clock-sh7786.c | 56 static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18, variable
60 .divisors = div2,
61 .nr_divisors = ARRAY_SIZE(div2),
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| /arch/arm/mach-shmobile/ |
| D | clock-r8a73a4.c | 95 SH_CLK_RATIO(div2, 1, 2);
98 SH_FIXED_RATIO_CLK(main_div2_clk, main_clk, div2);
99 SH_FIXED_RATIO_CLK(extal1_div2_clk, extal1_clk, div2);
100 SH_FIXED_RATIO_CLK(extal2_div2_clk, extal2_clk, div2);
189 SH_FIXED_RATIO_CLK(pll1_div2_clk, pll1_clk, div2);
331 SH_FIXED_RATIO_CLK(pll0_div2_clk, pll0_clk, div2);
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| D | clock-sh7372.c | 87 SH_CLK_RATIO(div2, 1, 2);
89 SH_FIXED_RATIO_CLKg(sh7372_dv_clki_div2_clk, sh7372_dv_clki_clk, div2);
90 SH_FIXED_RATIO_CLK(extal1_div2_clk, sh7372_extal1_clk, div2);
91 SH_FIXED_RATIO_CLK(extal2_div2_clk, sh7372_extal2_clk, div2);
92 SH_FIXED_RATIO_CLK(extal2_div4_clk, extal2_div2_clk, div2);
124 SH_FIXED_RATIO_CLK(pllc1_div2_clk, pllc1_clk, div2);
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| D | clock-r8a7740.c | 102 SH_CLK_RATIO(div2, 1, 2);
105 SH_FIXED_RATIO_CLK(extal1_div2_clk, extal1_clk, div2);
108 SH_FIXED_RATIO_CLK(extal2_div2_clk, extal2_clk, div2);
119 SH_FIXED_RATIO_CLK(system_div2_clk, system_clk, div2);
156 SH_FIXED_RATIO_CLK(pllc1_div2_clk, pllc1_clk, div2);
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| D | clock-sh73a0.c | 153 SH_CLK_RATIO(div2, 1, 2);
157 SH_FIXED_RATIO_CLK(extal1_div2_clk, sh73a0_extal1_clk, div2);
158 SH_FIXED_RATIO_CLK(extal2_div2_clk, sh73a0_extal2_clk, div2);
159 SH_FIXED_RATIO_CLK(main_div2_clk, main_clk, div2);
160 SH_FIXED_RATIO_CLK(pll1_div2_clk, pll1_clk, div2);
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| /arch/mips/alchemy/common/ |
| D | clock.c | 356 long div1, div2; in alchemy_calc_div() local
367 div2 = (div1 / scale) - 1; /* value to write to register */ in alchemy_calc_div()
369 if (div2 > maxdiv) in alchemy_calc_div()
370 div2 = maxdiv; in alchemy_calc_div()
372 *rv = div2; in alchemy_calc_div()
374 div1 = ((div2 + 1) * scale); in alchemy_calc_div()
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