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Searched refs:enable_reg (Results 1 – 18 of 18) sorted by relevance

/arch/arm/mach-ep93xx/
Dclock.c35 void __iomem *enable_reg; member
56 .enable_reg = EP93XX_SYSCON_DEVCFG,
63 .enable_reg = EP93XX_SYSCON_DEVCFG,
70 .enable_reg = EP93XX_SYSCON_DEVCFG,
91 .enable_reg = EP93XX_SYSCON_PWRCNT,
97 .enable_reg = EP93XX_SYSCON_KEYTCHCLKDIV,
112 .enable_reg = EP93XX_SYSCON_VIDCLKDIV,
119 .enable_reg = EP93XX_SYSCON_I2SCLKDIV,
127 .enable_reg = EP93XX_SYSCON_I2SCLKDIV,
135 .enable_reg = EP93XX_SYSCON_I2SCLKDIV,
[all …]
/arch/arm/mach-omap2/
Dcclock3xxx_data.c187 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
220 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
303 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
453 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
481 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
526 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
582 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
736 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
753 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
767 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
[all …]
Dclock3517.c55 *idlest_reg = (__force void __iomem *)(clk->enable_reg); in am35xx_clk_find_idlest()
78 *other_reg = (__force void __iomem *)(clk->enable_reg); in am35xx_clk_find_companion()
107 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); in am35xx_clk_ipss_find_idlest()
Dclock.c253 r = ((__force u32)clk->enable_reg ^ (CM_FCLKEN ^ CM_ICLKEN)); in omap2_clk_dflt_find_companion()
278 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); in omap2_clk_dflt_find_idlest()
320 if (unlikely(clk->enable_reg == NULL)) { in omap2_dflt_clk_enable()
328 v = omap2_clk_readl(clk, clk->enable_reg); in omap2_dflt_clk_enable()
333 omap2_clk_writel(v, clk, clk->enable_reg); in omap2_dflt_clk_enable()
334 v = omap2_clk_readl(clk, clk->enable_reg); /* OCP barrier */ in omap2_dflt_clk_enable()
362 if (!clk->enable_reg) { in omap2_dflt_clk_disable()
372 v = omap2_clk_readl(clk, clk->enable_reg); in omap2_dflt_clk_disable()
377 omap2_clk_writel(v, clk, clk->enable_reg); in omap2_dflt_clk_disable()
409 if (unlikely(clk->enable_reg)) in omap2_clkops_enable_clkdm()
[all …]
Dclock34xx.c47 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); in omap3430es2_clk_ssi_find_idlest()
85 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); in omap3430es2_clk_dss_usbhost_find_idlest()
122 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); in omap3430es2_clk_hsotgusb_find_idlest()
Dclkt_iclk.c32 ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN)); in omap2_clkt_iclk_allow_idle()
46 ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN)); in omap2_clkt_iclk_deny_idle()
Dclock.h95 .enable_reg = _enable_reg, \
/arch/arm/mach-omap1/
Dclock_data.c101 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
113 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1),
135 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
154 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
165 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
178 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
191 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
215 .enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL),
237 .enable_reg = DSP_IDLECT2,
249 .enable_reg = DSP_IDLECT2,
[all …]
Dclock.c46 unsigned int val = __raw_readl(clk->enable_reg); in omap1_uart_recalc()
334 val = __raw_readl(clk->enable_reg); in omap1_set_uart_rate()
341 __raw_writel(val, clk->enable_reg); in omap1_set_uart_rate()
360 ratio_bits |= __raw_readw(clk->enable_reg) & ~0xfd; in omap1_set_ext_clk_rate()
361 __raw_writew(ratio_bits, clk->enable_reg); in omap1_set_ext_clk_rate()
400 ratio_bits = __raw_readw(clk->enable_reg) & ~1; in omap1_init_ext_clk()
401 __raw_writew(ratio_bits, clk->enable_reg); in omap1_init_ext_clk()
457 if (unlikely(clk->enable_reg == NULL)) { in omap1_clk_enable_generic()
464 regval32 = __raw_readl(clk->enable_reg); in omap1_clk_enable_generic()
466 __raw_writel(regval32, clk->enable_reg); in omap1_clk_enable_generic()
[all …]
Dclock.h149 void __iomem *enable_reg; member
/arch/arm/mach-lpc32xx/
Dclock.c547 tmp = __raw_readl(clk->enable_reg); in local_onoff_enable()
554 __raw_writel(tmp, clk->enable_reg); in local_onoff_enable()
563 .enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
570 .enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
577 .enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
584 .enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
591 .enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
598 .enable_reg = LPC32XX_CLKPWR_TIMER_CLK_CTRL,
605 .enable_reg = LPC32XX_CLKPWR_DEBUG_CTRL,
612 .enable_reg = LPC32XX_CLKPWR_DMA_CLK_CTRL,
[all …]
Dclock.h34 void __iomem *enable_reg; member
/arch/arm/mach-shmobile/
Dclock-r8a73a4.c178 .enable_reg = (void __iomem *)reg, \
249 frqcrc = clk->mapped_reg + (FRQCRC - (u32)clk->enable_reg); in zclk_set_rate()
303 void __iomem *frqcrc = FRQCRC - (u32)clk->enable_reg + clk->mapped_reg; in zclk_recalc()
323 .enable_reg = (void __iomem *)FRQCRB,
338 .enable_reg = (void __iomem *)FRQCRB,
456 .enable_reg = (void __iomem *)_reg, \
Dclock-sh73a0.c103 mult = (((__raw_readl(clk->enable_reg) >> 24) & 0x3f) + 1); in pll_recalc()
108 if (__raw_readl(clk->enable_reg) & (1 << 20)) in pll_recalc()
124 .enable_reg = (void __iomem *)PLL0CR,
132 .enable_reg = (void __iomem *)PLL1CR,
140 .enable_reg = (void __iomem *)PLL2CR,
148 .enable_reg = (void __iomem *)PLL3CR,
Dclock-r8a7740.c132 mult = ((__raw_readl(clk->enable_reg) >> 24) & 0x7f) + 1; in pllc01_recalc()
145 .enable_reg = (void __iomem *)FRQCRC,
152 .enable_reg = (void __iomem *)FRQCRA,
Dclock-sh7372.c100 mult = (((__raw_readl(clk->enable_reg) >> 24) & 0x3f) + 1) * 2; in pllc01_recalc()
113 .enable_reg = (void __iomem *)FRQCRC,
120 .enable_reg = (void __iomem *)FRQCRA,
/arch/arm/plat-omap/
Ddma.c1223 u32 val, enable_reg; in omap2_dma_irq_handler() local
1232 enable_reg = p->dma_read(IRQENABLE_L0, 0); in omap2_dma_irq_handler()
1233 val &= enable_reg; /* Dispatch only relevant interrupts */ in omap2_dma_irq_handler()
/arch/sh/drivers/pci/
Dpcie-sh7786.c239 clk->enable_reg = (void __iomem *)(chan->reg_base + SH4A_PCIEPHYCTLR); in pcie_clk_init()