Searched refs:errata (Results 1 – 25 of 26) sorted by relevance
12
122 u32 errata; member339 if (timer->errata & OMAP_TIMER_ERRATA_I103_I767) { in __omap_dm_timer_enable_posted()362 u32 errata) in __omap_dm_timer_override_errata() argument364 timer->errata &= ~errata; in __omap_dm_timer_override_errata()
125 unsigned errata = 0; in configure_dma_errata() local204 return errata; in configure_dma_errata()233 p.errata = configure_dma_errata(); in omap2_system_dma_init_dev()
334 clkev.errata = omap_dm_timer_get_errata(); in omap2_gp_clockevent_init()464 clksrc.errata = omap_dm_timer_get_errata(); in omap2_gptimer_clocksource_init()
316 bool "OMAP4 errata: Async Bridge Corruption"329 The work-around for this errata needs all the initiators connected
144 # 40x errata/workaround config symbols, selected by the CPU models above146 # All 405-based cores up until the 405GPR and 405EP have this errata.150 # All 40x-based cores, up until the 405GPR and 405EP have this errata.
19 obj-y += cvmx-helper-errata.o cvmx-helper-jtag.o
247 unsigned errata = 0; in configure_dma_errata() local256 return errata; in configure_dma_errata()341 p.errata = configure_dma_errata(); in omap1_system_dma_init()
156 @ work around errata of OMAP1510 PDE bit for TC shut down
675 const char *errata[8]; in l2c310_fixup() local684 errata[n++] = "588369"; in l2c310_fixup()691 errata[n++] = "727915"; in l2c310_fixup()701 errata[n++] = "752271"; in l2c310_fixup()708 errata[n++] = "753970"; in l2c310_fixup()712 errata[n++] = "769419"; in l2c310_fixup()719 pr_cont(" %s", errata[i]); in l2c310_fixup()
921 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"933 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"941 this errata (fixed in r3p1).944 bool "PL310 errata: cache sync operation may be faulty"958 bool "PL310 errata: no automatic Store Buffer drain"
100 teqeq r2, r1 @ test for errata affected core and if so...
53 Enable workarounds for original MPC5200 errata. This is not required
356 bool "Enable linker work around for PPC476FPE errata #46"360 through pages (IBM errata #46). It requires a recent version368 # 44x errata/workaround config symbols, selected by the CPU models above
42 bool "Enable A5 and A9 only errata work-arounds"
43 # Disable instruction prefetching (Octeon Pass1 errata)
1064 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"1073 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"1082 bool "ARM errata: Stale prediction on replaced interworking branch"1098 bool "ARM errata: Processor deadlock when a false hazard is created"1112 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"1125 bool "ARM errata: DMB operation may be faulty"1138 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"1153 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"1163 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"1175 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"[all …]
4 bool "Enable CN63XXP1 errata workarounds"
69 ERRATA Known errata for this release
71 static u32 errata; variable1312 errata = p->errata; in omap_system_dma_probe()
851 timer->errata = pdata->timer_errata; in omap_dm_timer_probe()
206 /* See 35xx errata 2.1.1.128 in SPRZ278F */
308 bool "PentiumPro memory ordering errata workaround"311 Old PentiumPro multiprocessor systems had errata that could cause
109 .set UFLG_TMP,LV+121 | temporary for uflag errata
319 |** NOTE *** Bug fix for errata (0d43b #3)
245 menu "ARM errata workarounds via the alternatives framework"