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Searched refs:fclk (Results 1 – 8 of 8) sorted by relevance

/arch/sh/drivers/pci/
Dpcie-sh7786.c27 struct clk *fclk, phy_clk; member
223 port->fclk = clk_get(NULL, fclk_name); in pcie_clk_init()
224 if (IS_ERR(port->fclk)) { in pcie_clk_init()
225 ret = PTR_ERR(port->fclk); in pcie_clk_init()
229 clk_enable(port->fclk); in pcie_clk_init()
249 clk_disable(port->fclk); in pcie_clk_init()
250 clk_put(port->fclk); in pcie_clk_init()
/arch/arm/mach-omap2/
Dtimer.c290 timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh)); in omap_dm_timer_init_one()
291 if (IS_ERR(timer->fclk)) in omap_dm_timer_init_one()
292 return PTR_ERR(timer->fclk); in omap_dm_timer_init_one()
298 if (clk_get_parent(timer->fclk) != src) { in omap_dm_timer_init_one()
299 r = clk_set_parent(timer->fclk, src); in omap_dm_timer_init_one()
321 timer->rate = clk_get_rate(timer->fclk); in omap_dm_timer_init_one()
Dprm3xxx.c226 u32 wkst, fclk, iclk, clken; in omap3xxx_prm_clear_mod_irqs() local
239 fclk = omap2_cm_read_mod_reg(module, fclk_off); in omap3xxx_prm_clear_mod_irqs()
256 omap2_cm_write_mod_reg(fclk, module, fclk_off); in omap3xxx_prm_clear_mod_irqs()
/arch/arm/plat-omap/
Ddmtimer.c149 timer->fclk = clk_get(&timer->pdev->dev, "fck"); in omap_dm_timer_prepare()
150 if (WARN_ON_ONCE(IS_ERR(timer->fclk))) { in omap_dm_timer_prepare()
326 clk_put(timer->fclk); in omap_dm_timer_free()
408 if (timer && !IS_ERR(timer->fclk)) in omap_dm_timer_get_fclk()
409 return timer->fclk; in omap_dm_timer_get_fclk()
465 rate = clk_get_rate(timer->fclk); in omap_dm_timer_stop()
504 if (IS_ERR(timer->fclk)) in omap_dm_timer_set_source()
527 ret = clk_set_parent(timer->fclk, parent); in omap_dm_timer_set_source()
829 timer->fclk = ERR_PTR(-ENODEV); in omap_dm_timer_probe()
/arch/arm/plat-samsung/include/plat/
Dcpu-freq.h36 unsigned long fclk; member
/arch/arm/boot/dts/
Dzynq-parallella.dts38 fclk-enable = <0xf>;
Dzynq-7000.dtsi247 fclk-enable = <0>;
/arch/arm/plat-omap/include/plat/
Ddmtimer.h105 struct clk *fclk; member