Searched refs:fcr (Results 1 – 9 of 9) sorted by relevance
/arch/m68k/include/asm/ |
D | sun3xflop.h | 38 unsigned char fcr; member 85 unsigned char fcr = sun3x_fdc.fcr; in sun3x_82072_fd_outb() local 88 fcr |= (FCR_DSEL0 | FCR_MTRON); in sun3x_82072_fd_outb() 90 fcr &= ~(FCR_DSEL0 | FCR_MTRON); in sun3x_82072_fd_outb() 93 if(fcr != sun3x_fdc.fcr) { in sun3x_82072_fd_outb() 94 *(sun3x_fdc.fcr_r) = fcr; in sun3x_82072_fd_outb() 95 sun3x_fdc.fcr = fcr; in sun3x_82072_fd_outb() 226 sun3x_fdc.fcr = 0; in sun3xflop_init() 250 sun3x_fdc.fcr |= (FCR_DSEL0 | FCR_EJECT); in sun3x_eject() 251 *(sun3x_fdc.fcr_r) = sun3x_fdc.fcr; in sun3x_eject() [all …]
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/arch/powerpc/platforms/powermac/ |
D | feature.c | 168 unsigned long fcr; in ohare_htw_scc_enable() local 194 fcr = MACIO_IN32(OHARE_FCR); in ohare_htw_scc_enable() 196 if (!(fcr & OH_SCC_ENABLE)) { in ohare_htw_scc_enable() 197 fcr |= OH_SCC_ENABLE; in ohare_htw_scc_enable() 205 fcr &= ~HRW_SCC_TRANS_EN_N; in ohare_htw_scc_enable() 206 MACIO_OUT32(OHARE_FCR, fcr); in ohare_htw_scc_enable() 207 fcr |= (rmask = HRW_RESET_SCC); in ohare_htw_scc_enable() 208 MACIO_OUT32(OHARE_FCR, fcr); in ohare_htw_scc_enable() 210 fcr |= (rmask = OH_SCC_RESET); in ohare_htw_scc_enable() 211 MACIO_OUT32(OHARE_FCR, fcr); in ohare_htw_scc_enable() [all …]
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/arch/ia64/include/asm/sn/ |
D | ioc3.h | 23 char fcr; /* write only */ member 46 #define iu_fcr u3.fcr
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/arch/sh/include/asm/ |
D | smc37c93x.h | 91 #define fcr iir macro
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/arch/ia64/kernel/ |
D | paravirt.c | 427 __DEFINE_GET_AR(FCR, fcr) 510 __DEFINE_SET_AR(FCR, fcr) 708 IA64_NATIVE_PATCH_DEFINE_AR(fcr, fcr); 820 IA64_NATIVE_PATCH_BUNDLE_ELEM_AR(fcr, FCR),
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/arch/mips/include/asm/sn/ |
D | ioc3.h | 23 volatile u8 fcr; /* write only */ member 38 #define iu_fcr u3.fcr
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/arch/xtensa/variants/s6000/include/variant/ |
D | tie.h | 101 XCHAL_SA_REG(s,0,0,1,0, fcr, 4, 4, 4,0x03E8, ur,232, 32,0,0,0) \
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/arch/powerpc/include/asm/ |
D | fsl_lbc.h | 217 __be32 fcr; /**< Flash Command Register */ member
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/arch/ia64/kvm/ |
D | trampoline.S | 189 mov r16 = ar.fcr; \ 235 mov ar.fcr=r16; \
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