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/arch/mips/loongson/common/cs5536/
Dcs5536_ide.c21 u32 hi = 0, lo = value; in pci_ide_write_reg() local
25 _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo); in pci_ide_write_reg()
27 lo |= (0x03 << 4); in pci_ide_write_reg()
29 lo &= ~(0x03 << 4); in pci_ide_write_reg()
30 _wrmsr(GLIU_MSR_REG(GLIU_PAE), hi, lo); in pci_ide_write_reg()
34 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); in pci_ide_write_reg()
35 if (lo & SB_PARE_ERR_FLAG) { in pci_ide_write_reg()
36 lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG; in pci_ide_write_reg()
37 _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo); in pci_ide_write_reg()
43 _rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo); in pci_ide_write_reg()
[all …]
Dcs5536_acc.c21 u32 hi = 0, lo = value; in pci_acc_write_reg() local
25 _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo); in pci_acc_write_reg()
27 lo |= (0x03 << 8); in pci_acc_write_reg()
29 lo &= ~(0x03 << 8); in pci_acc_write_reg()
30 _wrmsr(GLIU_MSR_REG(GLIU_PAE), hi, lo); in pci_acc_write_reg()
34 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); in pci_acc_write_reg()
35 if (lo & SB_PARE_ERR_FLAG) { in pci_acc_write_reg()
36 lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG; in pci_acc_write_reg()
37 _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo); in pci_acc_write_reg()
43 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); in pci_acc_write_reg()
[all …]
Dcs5536_ohci.c21 u32 hi = 0, lo = value; in pci_ohci_write_reg() local
25 _rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo); in pci_ohci_write_reg()
35 _wrmsr(USB_MSR_REG(USB_OHCI), hi, lo); in pci_ohci_write_reg()
39 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); in pci_ohci_write_reg()
40 if (lo & SB_PARE_ERR_FLAG) { in pci_ohci_write_reg()
41 lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG; in pci_ohci_write_reg()
42 _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo); in pci_ohci_write_reg()
48 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); in pci_ohci_write_reg()
49 lo |= SOFT_BAR_OHCI_FLAG; in pci_ohci_write_reg()
50 _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); in pci_ohci_write_reg()
[all …]
Dcs5536_ehci.c21 u32 hi = 0, lo = value; in pci_ehci_write_reg() local
25 _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo); in pci_ehci_write_reg()
35 _wrmsr(USB_MSR_REG(USB_EHCI), hi, lo); in pci_ehci_write_reg()
39 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); in pci_ehci_write_reg()
40 if (lo & SB_PARE_ERR_FLAG) { in pci_ehci_write_reg()
41 lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG; in pci_ehci_write_reg()
42 _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo); in pci_ehci_write_reg()
48 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); in pci_ehci_write_reg()
49 lo |= SOFT_BAR_EHCI_FLAG; in pci_ehci_write_reg()
50 _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); in pci_ehci_write_reg()
[all …]
Dcs5536_isa.c55 u32 hi, lo; in divil_lbar_enable() local
63 _rdmsr(DIVIL_MSR_REG(offset), &hi, &lo); in divil_lbar_enable()
65 _wrmsr(DIVIL_MSR_REG(offset), hi, lo); in divil_lbar_enable()
74 u32 hi, lo; in divil_lbar_disable() local
78 _rdmsr(DIVIL_MSR_REG(offset), &hi, &lo); in divil_lbar_disable()
80 _wrmsr(DIVIL_MSR_REG(offset), hi, lo); in divil_lbar_disable()
90 u32 hi = 0, lo = value; in pci_isa_write_bar() local
93 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); in pci_isa_write_bar()
94 lo |= soft_bar_flag[n]; in pci_isa_write_bar()
95 _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); in pci_isa_write_bar()
[all …]
/arch/ia64/lib/
Dcarta_random.S15 #define lo r8 macro
30 zxt4 lo = t0
38 add lo = lo, t0
40 cmp.gtu p6, p0 = lo, m
42 (p6) and lo = lo, m
44 (p6) add lo = 1, lo
46 add lo = lo, t1
48 cmp.gtu p6, p0 = lo, m
50 (p6) and lo = lo, m
52 (p6) add lo = 1, lo
/arch/powerpc/boot/
Dmv64x60.c155 u32 lo; member
162 u32 lo; member
199 .lo = MV64x60_CPU2MEM_0_BASE,
203 .lo = MV64x60_CPU2MEM_1_BASE,
207 .lo = MV64x60_CPU2MEM_2_BASE,
211 .lo = MV64x60_CPU2MEM_3_BASE,
218 .lo = MV64x60_ENET2MEM_0_BASE,
222 .lo = MV64x60_ENET2MEM_1_BASE,
226 .lo = MV64x60_ENET2MEM_2_BASE,
230 .lo = MV64x60_ENET2MEM_3_BASE,
[all …]
/arch/x86/kernel/cpu/
Dcentaur.c21 u32 lo, hi; in init_c3() local
29 rdmsr(MSR_VIA_FCR, lo, hi); in init_c3()
30 lo |= ACE_FCR; /* enable ACE unit */ in init_c3()
31 wrmsr(MSR_VIA_FCR, lo, hi); in init_c3()
37 rdmsr(MSR_VIA_RNG, lo, hi); in init_c3()
38 lo |= RNG_ENABLE; /* enable RNG unit */ in init_c3()
39 wrmsr(MSR_VIA_RNG, lo, hi); in init_c3()
51 rdmsr(MSR_VIA_FCR, lo, hi); in init_c3()
52 lo |= (1<<1 | 1<<7); in init_c3()
53 wrmsr(MSR_VIA_FCR, lo, hi); in init_c3()
[all …]
/arch/x86/kernel/cpu/mcheck/
Dwinchip.c24 u32 lo, hi; in winchip_mcheck_init() local
30 rdmsr(MSR_IDT_FCR1, lo, hi); in winchip_mcheck_init()
31 lo |= (1<<2); /* Enable EIERRINT (int 18 MCE) */ in winchip_mcheck_init()
32 lo &= ~(1<<4); /* Enable MCE */ in winchip_mcheck_init()
33 wrmsr(MSR_IDT_FCR1, lo, hi); in winchip_mcheck_init()
/arch/x86/platform/intel-mid/
Dmrfl.c22 u32 lo, hi, ratio, fsb, bus_freq; in tangier_calibrate_tsc() local
29 rdmsr(MSR_PLATFORM_INFO, lo, hi); in tangier_calibrate_tsc()
30 pr_debug("IA32 PLATFORM_INFO is 0x%x : %x\n", hi, lo); in tangier_calibrate_tsc()
32 ratio = (lo >> 8) & 0xFF; in tangier_calibrate_tsc()
40 rdmsr(MSR_FSB_FREQ, lo, hi); in tangier_calibrate_tsc()
42 hi, lo); in tangier_calibrate_tsc()
44 bus_freq = lo & 0x7; in tangier_calibrate_tsc()
Dmfld.c33 u32 lo, hi, ratio, fsb; in mfld_calibrate_tsc() local
35 rdmsr(MSR_IA32_PERF_STATUS, lo, hi); in mfld_calibrate_tsc()
36 pr_debug("IA32 perf status is 0x%x, 0x%0x\n", lo, hi); in mfld_calibrate_tsc()
44 rdmsr(MSR_FSB_FREQ, lo, hi); in mfld_calibrate_tsc()
45 if ((lo & 0x7) == 0x7) in mfld_calibrate_tsc()
/arch/metag/kernel/
Dsys_metag.c24 #define merge_64(hi, lo) ((((unsigned long long)(hi)) << 32) + \ argument
25 ((lo) & 0xffffffffUL))
107 asmlinkage long sys_truncate64_metag(const char __user *path, unsigned long lo, in sys_truncate64_metag() argument
110 return sys_truncate64(path, merge_64(hi, lo)); in sys_truncate64_metag()
113 asmlinkage long sys_ftruncate64_metag(unsigned int fd, unsigned long lo, in sys_ftruncate64_metag() argument
116 return sys_ftruncate64(fd, merge_64(hi, lo)); in sys_ftruncate64_metag()
128 asmlinkage long sys_readahead_metag(int fd, unsigned long lo, unsigned long hi, in sys_readahead_metag() argument
131 return sys_readahead(fd, merge_64(hi, lo), count); in sys_readahead_metag()
135 size_t count, unsigned long lo, in sys_pread64_metag() argument
138 return sys_pread64(fd, buf, count, merge_64(hi, lo)); in sys_pread64_metag()
[all …]
/arch/frv/kernel/
Dhead-uc-fr401.S59 setlo %lo(__400_DBR0),gr14
89 setlo %lo(__400_LGCR),gr4
91 setlo %lo(__400_LSBR),gr10
93 setlo %lo(__400_LCR),gr11
101 setlo %lo(__region_CS1),gr4
103 setlo %lo(__region_CS1_M),gr5
105 setlo %lo(__region_CS1_C),gr6
110 setlo %lo(__region_CS2),gr4
112 setlo %lo(__region_CS2_M),gr5
114 setlo %lo(__region_CS2_C),gr6
[all …]
Dhead-mmu-fr451.S60 setlo %lo(__400_DBR0),gr14
82 setlo %lo(__400_LGCR),gr4
84 setlo %lo(__400_LSBR),gr10
86 setlo %lo(__400_LCR),gr11
94 setlo %lo(__region_CS1),gr4
96 setlo %lo(__region_CS1_M),gr5
98 setlo %lo(__region_CS1_C),gr6
103 setlo %lo(__region_CS2),gr4
105 setlo %lo(__region_CS2_M),gr5
107 setlo %lo(__region_CS2_C),gr6
[all …]
Dhead-uc-fr555.S58 setlo %lo(__551_DARS0),gr14
81 setlo %lo(__551_LSBR),gr10
83 setlo %lo(__551_LCR),gr11
87 setlo %lo(__region_CS1),gr4
89 setlo %lo(__region_CS1_M),gr5
91 setlo %lo(__region_CS1_C),gr6
96 setlo %lo(__region_CS2),gr4
98 setlo %lo(__region_CS2_M),gr5
100 setlo %lo(__region_CS2_C),gr6
105 setlo %lo(__region_CS3),gr4
[all …]
/arch/mips/loongson/lemote-2f/
Dreset.c48 u32 hi, lo; in fl2f_reboot() local
49 _rdmsr(DIVIL_MSR_REG(DIVIL_SOFT_RESET), &hi, &lo); in fl2f_reboot()
50 lo |= 0x00000001; in fl2f_reboot()
51 _wrmsr(DIVIL_MSR_REG(DIVIL_SOFT_RESET), hi, lo); in fl2f_reboot()
57 u32 hi, lo, val; in fl2f_shutdown() local
61 _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_GPIO), &hi, &lo); in fl2f_shutdown()
62 gpio_base = lo & 0xff00; in fl2f_shutdown()
/arch/blackfin/mach-common/
Ddpmc_modes.S20 P0.L = lo(PLL_CTL);
39 P0.L = lo(PLL_CTL);
69 P3.L = lo(VR_CTL);
107 P0.L = lo(PLL_DIV);
113 P0.L = lo(PLL_CTL);
124 P0.L = lo(VR_CTL);
145 P0.L = lo(PLL_CTL);
161 P0.L = lo(VR_CTL);
172 P0.L = lo(PLL_DIV);
176 P0.L = lo(PLL_CTL);
[all …]
/arch/x86/kernel/
Dtsc_msr.c85 u32 lo, hi, ratio, freq_id, freq; in try_msr_calibrate_tsc() local
94 rdmsr(MSR_PLATFORM_INFO, lo, hi); in try_msr_calibrate_tsc()
95 ratio = (lo >> 8) & 0xff; in try_msr_calibrate_tsc()
97 rdmsr(MSR_IA32_PERF_STATUS, lo, hi); in try_msr_calibrate_tsc()
106 rdmsr(MSR_FSB_FREQ, lo, hi); in try_msr_calibrate_tsc()
107 freq_id = lo & 0x7; in try_msr_calibrate_tsc()
/arch/sparc/kernel/
Dtrampoline_64.S108 1: ldstub [%g2 + %lo(prom_entry_lock)], %g1
116 or %g1, %lo(tramp_stack), %g1
130 ldx [%l4 + %lo(kern_locked_tte_data)], %l4
133 lduw [%l6 + %lo(num_kernel_image_mappings)], %l6
144 or %g2, %lo(call_method), %g2
151 or %g2, %lo(itlb_load), %g2
154 lduw [%g2 + %lo(prom_mmu_ihandle_cache)], %g2
170 or %g2, %lo(p1275buf), %g2
177 or %g2, %lo(call_method), %g2
184 or %g2, %lo(dtlb_load), %g2
[all …]
Dsys32.S19 jmpl %g1 + %lo(SYSCALL), %g0; \
27 jmpl %g1 + %lo(SYSCALL), %g0; \
36 jmpl %g1 + %lo(SYSCALL), %g0; \
56 jmpl %g1 + %lo(sys_mmap), %g0
69 or %g2, %lo(__socketcall_table_begin), %g2
84 jmpl %g1 + %lo(sys_socket), %g0
93 jmpl %g1 + %lo(sys_bind), %g0
102 jmpl %g1 + %lo(sys_connect), %g0
110 jmpl %g1 + %lo(sys_listen), %g0
120 jmpl %g1 + %lo(sys_accept), %g0
[all …]
/arch/mips/sgi-ip22/
Dip28-berr.c53 u32 lo; member
71 tag[0].lo = read_c0_taglo(); /* PA[35:18], VA[13:12] */ in save_cache_tags()
74 tag[1].lo = read_c0_taglo(); /* PA[35:18], VA[13:12] */ in save_cache_tags()
89 tag[0].lo = read_c0_taglo(); /* PA[35:12] */ in save_cache_tags()
92 tag[1].lo = read_c0_taglo(); /* PA[35:12] */ in save_cache_tags()
105 tag[0].lo = read_c0_taglo(); /* PA[35:12] */ in save_cache_tags()
108 tag[1].lo = read_c0_taglo(); /* PA[35:12] */ in save_cache_tags()
178 if ((cache_tags.tagd[i][0].lo & 0x0fffff00) != scw && in print_cache_tags()
179 (cache_tags.tagd[i][1].lo & 0x0fffff00) != scw) in print_cache_tags()
183 cache_tags.tagd[i][0].hi, cache_tags.tagd[i][0].lo, in print_cache_tags()
[all …]
/arch/sparc/lib/
DNGpatch.S10 or %g1, %lo(NEW), %g1; \
12 or %g2, %lo(OLD), %g2; \
17 or %g3, %lo(BRANCH_ALWAYS), %g3; \
21 or %g3, %lo(NOP), %g3; \
DU3patch.S10 or %g1, %lo(NEW), %g1; \
12 or %g2, %lo(OLD), %g2; \
17 or %g3, %lo(BRANCH_ALWAYS), %g3; \
21 or %g3, %lo(NOP), %g3; \
DGENpatch.S10 or %g1, %lo(NEW), %g1; \
12 or %g2, %lo(OLD), %g2; \
17 or %g3, %lo(BRANCH_ALWAYS), %g3; \
21 or %g3, %lo(NOP), %g3; \
DNG2patch.S10 or %g1, %lo(NEW), %g1; \
12 or %g2, %lo(OLD), %g2; \
17 or %g3, %lo(BRANCH_ALWAYS), %g3; \
21 or %g3, %lo(NOP), %g3; \

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