| /arch/mips/ar7/ |
| D | clock.c | 83 u32 mul; member
112 int *postdiv, int *mul) in approximate() argument
121 *mul = i; in approximate()
129 int *mul) in calculate() argument
136 *mul = target / tmp_gcd; in calculate()
138 if ((*mul < 1) || (*mul >= 16)) in calculate()
144 if (base / *prediv * *mul / *postdiv != target) { in calculate()
145 approximate(base, target, prediv, postdiv, mul); in calculate()
146 tmp_freq = base / *prediv * *mul / *postdiv; in calculate()
153 *prediv, *postdiv, *mul); in calculate()
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| /arch/arm/lib/ |
| D | muldi3.S | 31 mul xh, yl, xh
38 mul yh, xl, yh
39 mul xl, yl, xl
40 mul ip, yl, ip
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| D | delay-loop.S | 26 mul r0, r2, r0
35 mul r0, r2, r0 @ max = 2^32-1
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| D | lib1funcs.S | 332 mul r3, r0, r2
345 mul r3, r0, r2
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| /arch/mips/ralink/ |
| D | mt7620.c | 141 mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div) in mt7620_calc_rate() argument
146 t *= mul; in mt7620_calc_rate()
184 u32 mul; in mt7620_get_cpu_pll_rate() local
194 mul = (reg >> CPLL_CFG0_PLL_MULT_RATIO_SHIFT) & in mt7620_get_cpu_pll_rate()
196 mul += 24; in mt7620_get_cpu_pll_rate()
198 mul *= 2; in mt7620_get_cpu_pll_rate()
205 return mt7620_calc_rate(xtal_rate, mul, mt7620_clk_divider[div]); in mt7620_get_cpu_pll_rate()
227 u32 mul; in mt7620_get_cpu_rate() local
232 mul = reg & CPU_SYS_CLKCFG_CPU_FFRAC_MASK; in mt7620_get_cpu_rate()
236 return mt7620_calc_rate(pll_rate, mul, div); in mt7620_get_cpu_rate()
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| /arch/arm/mach-shmobile/ |
| D | clock.h | 25 int mul; member
31 .mul = m, \
51 (p)->mul = m; \
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| D | clock.c | 59 return clk->parent->rate / p->div * p->mul; in shmobile_fixed_ratio_clk_recalc()
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| /arch/m68k/fpsp040/ |
| D | binstr.S | 16 | bit 63. The fraction is multiplied by 10 using a mul by 2
17 | shift and a mul by 8 shift. The bits shifted out of the
51 | d2: upper 32-bits of fraction for mul by 8
52 | d3: lower 32-bits of fraction for mul by 8
53 | d4: upper 32-bits of fraction for mul by 2
54 | d5: lower 32-bits of fraction for mul by 2
97 asll #1,%d5 |mul d5 by 2
98 roxll #1,%d4 |mul d4 by 2
100 addxw %d6,%d1 |add in extend from mul by 2
102 | A5. Add mul by 8 to mul by 2. D1 contains the digit formed.
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| D | decbin.S | 62 | Clean up and return. Check if the final mul or div resulted
125 | 2. Calculate absolute value of exponent in d1 by mul and add.
153 mulul #TEN,%d1 |mul partial product by one digit place
463 bccs e_next |if zero, skip the mul
464 fmulx (%a1,%d3),%fp1 |mul by 10**(d3_bit_no)
483 beqs mul |if clear, go to multiply
487 mul: label
493 | If the final mul/div in decbin incurred an inex exception,
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| D | bindec.S | 254 fmulx LOG2UP1,%fp0 |if neg, mul by LOG2UP1
258 fmulx LOG2,%fp0 |if pos, mul by LOG2
650 bccs l_next |if zero, skip the mul
651 fmulx (%a1,%d3),%fp2 |mul by 10**(d3_bit_no)
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| /arch/arm/boot/compressed/ |
| D | ll_char_wr.S | 69 mul r7, r2, r7
74 mul r7, r2, r7
88 mul r4, r2, ip
91 mul ip, r2, ip @ avoid r4
98 mul r4, r2, ip
101 mul ip, r2, ip @ avoid r4
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| /arch/unicore32/lib/ |
| D | delay.S | 28 mul r0, r2, r0
34 mul r0, r2, r0 @ max = 2^32-1
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| /arch/openrisc/ |
| D | Makefile | 30 KBUILD_CFLAGS += $(call cc-option,-mhard-mul)
32 KBUILD_CFLAGS += $(call cc-option,-msoft-mul)
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| D | Kconfig | 93 bool "Have instruction l.mul for hardware multiply"
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| /arch/mips/kernel/ |
| D | cps-vec.S | 107 mul t1, t1, t0
108 mul t1, t1, t2
134 mul t1, t1, t0
135 mul t1, t1, t2
307 mul t0, t0, t1
336 mul v0, t9, t1
387 mul t0, t0, ta1
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| /arch/avr32/mach-at32ap/ |
| D | hsmc.c | 38 unsigned long mul; in smc_set_timing() local
57 mul = (clk_get_rate(hsmc->mck) / 10000) << 16; in smc_set_timing()
58 mul /= 100000; in smc_set_timing()
60 #define ns2cyc(x) ((((x) * mul) + 65535) >> 16) in smc_set_timing()
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| D | at32ap700x.c | 117 unsigned long div, mul, rate; in pll_get_rate() local
120 mul = PM_BFEXT(PLLMUL, control) + 1; in pll_get_rate()
124 rate *= mul; in pll_get_rate()
132 unsigned long mul; in pll_set_rate() local
161 mul = (rate + pll_in / 2) / pll_in; in pll_set_rate()
163 if (mul == 0) in pll_set_rate()
166 actual = pll_in * mul; in pll_set_rate()
170 mul_best_fit = mul; in pll_set_rate()
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| /arch/arm/mach-at91/ |
| D | clock.c | 590 unsigned mul, div; in at91_pll_rate() local
594 mul = AT91_PMC3_MUL_GET(reg); in at91_pll_rate()
596 mul = AT91_PMC_MUL_GET(reg); in at91_pll_rate()
598 if (div && mul) { in at91_pll_rate()
600 freq *= mul + 1; in at91_pll_rate()
619 unsigned i, div = 0, mul = 0, diff = 1 << 30; in at91_pll_calc() local
644 if (cpu_is_at91sam9g20() && mul > 63) in at91_pll_calc()
657 mul = mul1; in at91_pll_calc()
664 return ret | ((mul - 1) << 16) | div; in at91_pll_calc()
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| /arch/sh/lib/ |
| D | div64.S | 28 mul.l r6, r2
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| /arch/powerpc/platforms/512x/ |
| D | clock-commonclk.c | 228 int mul, int div) in mpc512x_clk_factor() argument
234 mul, div); in mpc512x_clk_factor()
707 int mul, div; in mpc512x_clk_setup_clock_tree() local
778 mul = get_cpmf_mult_x2(); in mpc512x_clk_setup_clock_tree()
780 clks[MPC512x_CLK_E300] = mpc512x_clk_factor("e300", "csb", mul, div); in mpc512x_clk_setup_clock_tree()
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| /arch/mips/include/asm/octeon/ |
| D | cvmx-spxx-defs.h | 291 uint64_t mul:1; member
301 uint64_t mul:1;
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| /arch/mips/netlogic/common/ |
| D | reset.S | 190 mul t3, t2, t1 /* t3 = node * 0x40000 */
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| /arch/arm64/kernel/vdso/ |
| D | gettimeofday.S | 75 mul \res, \res, \mult
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| /arch/m68k/ifpsp060/src/ |
| D | ilsp.S | 480 # _060LSP__imulu64_(): Emulate 64-bit unsigned mul instruction #
481 # _060LSP__imuls64_(): Emulate 64-bit signed mul instruction. #
484 # and therefore does not work exactly like the 680X0 mul{s,u}.l #
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| /arch/microblaze/boot/dts/ |
| D | system.dts | 125 xlnx,use-hw-mul = <0x2>;
|