Searched refs:num_parents (Results 1 – 16 of 16) sorted by relevance
| /arch/arm/mach-imx/ |
| D | clk.h | 66 const char **parent_names, int num_parents);
74 int num_parents, void (*fixup)(u32 *val));
111 u8 shift, u8 width, const char **parents, int num_parents) in imx_clk_mux() argument
113 return clk_register_mux(NULL, name, parents, num_parents, in imx_clk_mux()
120 int num_parents, unsigned long flags) in imx_clk_mux_flags() argument
122 return clk_register_mux(NULL, name, parents, num_parents, in imx_clk_mux_flags()
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| D | clk-fixup-mux.c | 76 int num_parents, void (*fixup)(u32 *val)) in imx_clk_fixup_mux() argument
92 init.num_parents = num_parents; in imx_clk_fixup_mux()
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| D | clk-busy.c | 106 init.num_parents = 1; in imx_clk_busy_divider()
157 const char **parent_names, int num_parents) in imx_clk_busy_mux() argument
180 init.num_parents = num_parents; in imx_clk_busy_mux()
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| D | clk-gate-exclusive.c | 81 init.num_parents = parent ? 1 : 0; in imx_clk_gate_exclusive()
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| D | clk-pllv1.c | 117 init.num_parents = 1; in imx_clk_pllv1()
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| D | clk-pfd.c | 149 init.num_parents = 1; in imx_clk_pfd()
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| D | clk-fixup-div.c | 114 init.num_parents = parent ? 1 : 0; in imx_clk_fixup_divider()
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| D | clk-gate2.c | 136 init.num_parents = parent_name ? 1 : 0; in clk_register_gate2()
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| D | clk-pllv2.c | 257 init.num_parents = 1; in imx_clk_pllv2()
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| D | clk-pllv3.c | 323 init.num_parents = 1; in imx_clk_pllv3()
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| /arch/arm/mach-omap2/ |
| D | clock.h | 47 .num_parents = ARRAY_SIZE(_parent_array_name), \
57 .num_parents = ARRAY_SIZE(_parent_array_name), \
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| D | clkt2xxx_virt_prcm_set.c | 247 init.num_parents = 1; in omap2xxx_clkt_vps_init()
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| D | cclock3xxx_data.c | 466 .num_parents = ARRAY_SIZE(dpll4_m5x2_ck_parent_names),
490 .num_parents = ARRAY_SIZE(cam_mclk_parent_names),
538 .num_parents = ARRAY_SIZE(dpll4_m2x2_ck_parent_names),
594 .num_parents = ARRAY_SIZE(dpll4_m3x2_ck_parent_names),
883 .num_parents = ARRAY_SIZE(dpll3_m3x2_ck_parent_names),
918 .num_parents = ARRAY_SIZE(dpll4_m4x2_ck_parent_names),
951 .num_parents = ARRAY_SIZE(dpll4_m6x2_ck_parent_names),
2494 .num_parents = ARRAY_SIZE(omap_96m_alwon_fck_3630_parent_names),
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| /arch/mips/alchemy/common/ |
| D | clock.c | 155 id.num_parents = 1; in alchemy_clk_setup_cpu()
240 id.num_parents = 1; in alchemy_clk_setup_aux()
738 id.num_parents = 2; in alchemy_clk_init_fgens()
743 id.num_parents = 3; in alchemy_clk_init_fgens()
945 id.num_parents = 7; in alchemy_clk_setup_imux()
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| /arch/arm/mach-msm/ |
| D | clock-pcom.c | 153 init.num_parents = 0; in msm_clock_pcom_probe()
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| /arch/arm/mach-vexpress/ |
| D | spc.c | 551 init.num_parents = 0; in ve_spc_clk_register()
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