/arch/powerpc/platforms/cell/ |
D | spu_priv1_mmio.c | 44 out_be64(&spu->priv1->int_mask_RW[class], old_mask & mask); in int_mask_and() 52 out_be64(&spu->priv1->int_mask_RW[class], old_mask | mask); in int_mask_or() 57 out_be64(&spu->priv1->int_mask_RW[class], mask); in int_mask_set() 67 out_be64(&spu->priv1->int_stat_RW[class], stat); in int_stat_clear() 90 out_be64(&spu->priv1->int_route_RW, route); in cpu_affinity_set() 105 out_be64(&spu->priv1->mfc_dsisr_RW, dsisr); in mfc_dsisr_set() 110 out_be64(&spu->priv1->mfc_sdr_RW, mfspr(SPRN_SDR1)); in mfc_sdr_setup() 115 out_be64(&spu->priv1->mfc_sr1_RW, sr1); in mfc_sr1_set() 125 out_be64(&spu->priv1->mfc_tclass_id_RW, tclass_id); in mfc_tclass_id_set() 135 out_be64(&spu->priv1->tlb_invalidate_entry_W, 0ul); in tlb_invalidate() [all …]
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D | interrupt.c | 86 out_be64(&iic->regs->prio, iic->eoi_stack[--iic->eoi_ptr]); in iic_eoi() 118 out_be64(&node_iic->iic_is, ack); in iic_ioexc_cascade() 131 out_be64(&node_iic->iic_is, ack); in iic_ioexc_cascade() 166 out_be64(&this_cpu_ptr(&cpu_iic)->regs->prio, 0xff); in iic_setup_cpu() 186 out_be64(&per_cpu(cpu_iic, cpu).regs->generate, (0xf - msg) << 4); in iic_message_pass() 308 out_be64(&iic->regs->prio, 0); in init_one_iic() 362 out_be64(&node_iic->iic_ir, in setup_iic() 369 out_be64(&node_iic->iic_is, 0xfffffffffffffffful); in setup_iic() 410 out_be64(&iic_regs->iic_ir, iic_ir); in iic_set_interrupt_routing()
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D | cbe_thermal.c | 146 out_be64(&pmd_regs->tm_tpr.val, reg_value); in store_throttle() 366 out_be64(&pmd_regs->tm_str2, str2); in init_default_values() 367 out_be64(&pmd_regs->tm_str1.val, str1.val); in init_default_values() 368 out_be64(&pmd_regs->tm_tpr.val, tpr.val); in init_default_values() 369 out_be64(&pmd_regs->tm_cr1.val, cr1.val); in init_default_values() 370 out_be64(&pmd_regs->tm_cr2, cr2); in init_default_values()
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D | spu_base.c | 86 out_be64(&priv2->slb_invalidate_all_W, 0UL); in spu_invalidate_slbs() 141 out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESTART_DMA_COMMAND); in spu_restart_dma() 155 out_be64(&priv2->slb_index_W, slbe); in spu_load_slb() 157 out_be64(&priv2->slb_esid_RW, 0); in spu_load_slb() 159 out_be64(&priv2->slb_vsid_RW, slb->vsid); in spu_load_slb() 161 out_be64(&priv2->slb_esid_RW, slb->esid); in spu_load_slb() 472 out_be64(&priv2->spu_chnlcntptr_RW, zero_list[i].channel); in spu_init_channels() 474 out_be64(&priv2->spu_chnldata_RW, 0); in spu_init_channels() 479 out_be64(&priv2->spu_chnlcntptr_RW, count_list[i].channel); in spu_init_channels() 480 out_be64(&priv2->spu_chnlcnt_RW, count_list[i].count); in spu_init_channels()
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D | pervasive.c | 127 out_be64(®s->pmcr, in_be64(®s->pmcr) | in cbe_pervasive_init()
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D | iommu.c | 157 out_be64(reg, val); in invalidate_tce_cache() 263 out_be64(iommu->xlate_regs + IOC_IO_ExcpStat, stat); in ioc_interrupt() 406 out_be64(iommu->xlate_regs + IOC_IO_ExcpStat, in cell_iommu_enable_hardware() 408 out_be64(iommu->xlate_regs + IOC_IO_ExcpMask, in cell_iommu_enable_hardware() 420 out_be64(iommu->xlate_regs + IOC_IOST_Origin, reg); in cell_iommu_enable_hardware() 425 out_be64(iommu->cmd_regs + IOC_IOCmd_Cfg, reg); in cell_iommu_enable_hardware() 798 out_be64(xregs + IOC_IOST_Origin, 0); in cell_disable_iommus() 802 out_be64(cregs + IOC_IOCmd_Cfg, val); in cell_disable_iommus()
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D | ras.c | 293 out_be64(®s->ras_esc_0, 0); in cbe_sysreset_hack()
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D | pmu.c | 51 out_be64(&(pmd_regs->reg), (((u64)_x) << 32)); \
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/arch/powerpc/platforms/cell/spufs/ |
D | switch.c | 202 out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE); in save_mfc_cntl() 285 out_be64(&priv2->mfc_control_RW, in halt_mfc_decr() 317 out_be64(&prob->spc_mssync_RW, 1UL); in do_mfc_mssync() 478 out_be64(&priv2->mfc_control_RW, in purge_mfc_queue() 543 out_be64(&priv2->spu_privcntl_RW, 0UL); in reset_spu_privcntl() 565 out_be64(&priv2->spu_lslr_RW, LS_ADDR_MASK); in reset_spu_lslr() 639 out_be64(&priv2->spu_chnlcntptr_RW, 1); in save_ch_part1() 645 out_be64(&priv2->spu_chnlcntptr_RW, idx); in save_ch_part1() 649 out_be64(&priv2->spu_chnldata_RW, 0UL); in save_ch_part1() 650 out_be64(&priv2->spu_chnlcnt_RW, 0UL); in save_ch_part1() [all …]
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D | hw_ops.c | 160 out_be64(&priv2->spu_cfg_RW, tmp); in spu_hw_signal1_type_set() 181 out_be64(&priv2->spu_cfg_RW, tmp); in spu_hw_signal2_type_set() 212 out_be64(&ctx->spu->priv2->spu_privcntl_RW, val); in spu_hw_privcntl_write() 296 out_be64(&prob->mfc_ea_W, cmd->ea); in spu_hw_send_mfc_command() 319 out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESTART_DMA_COMMAND); in spu_hw_restart_dma()
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D | run.c | 108 out_be64(mfc_cntl, MFC_CNTL_PURGE_DMA_REQUEST); in spu_setup_isolated() 121 out_be64(mfc_cntl, 0); in spu_setup_isolated()
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/arch/powerpc/include/asm/ |
D | io.h | 213 DEF_MMIO_OUT_D(out_be64, 64, std); 224 out_be64(addr, swab64(val)); in out_le64() 236 static inline void out_be64(volatile u64 __iomem *addr, u64 val) in out_be64() function 481 #define __do_writeq_be(val, addr) out_be64(PCI_FIX_ADDR(addr), val)
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/arch/powerpc/platforms/85xx/ |
D | smp.c | 314 out_be64((u64 *)(&spin_table->addr_h), in smp_85xx_kick_cpu()
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/arch/powerpc/platforms/powernv/ |
D | eeh-ioda.c | 122 out_be64(phb->regs + offset, val); in ioda_eeh_dbgfs_set()
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/arch/powerpc/platforms/pseries/ |
D | iommu.c | 77 out_be64(invalidate, start); in tce_invalidate_pSeries_sw()
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