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/arch/c6x/platforms/
Dpll.c33 if (clk->parent) in __clk_enable()
34 __clk_enable(clk->parent); in __clk_enable()
44 if (clk->parent) in __clk_disable()
45 __clk_disable(clk->parent); in __clk_disable()
132 int clk_set_parent(struct clk *clk, struct clk *parent) in clk_set_parent() argument
144 clk->parent = parent; in clk_set_parent()
146 list_add(&clk->childnode, &clk->parent->children); in clk_set_parent()
164 if (WARN(clk->parent && !clk->parent->rate, in clk_register()
166 clk->name, clk->parent->name)) in clk_register()
171 if (clk->parent) in clk_register()
[all …]
Dplldata.c41 .parent = &clkin1,
47 .parent = &c6x_soc_pll1.sysclks[0],
52 .parent = &c6x_soc_pll1.sysclks[0],
57 .parent = &c6x_soc_pll1.sysclks[0],
62 .parent = &c6x_soc_pll1.sysclks[0],
67 .parent = &c6x_soc_pll1.sysclks[0],
72 .parent = &c6x_soc_pll1.sysclks[0],
77 .parent = &c6x_soc_pll1.sysclks[0],
82 .parent = &c6x_soc_pll1.sysclks[0],
87 .parent = &c6x_soc_pll1.sysclks[0],
[all …]
/arch/mips/jz4740/
Dclock.c219 return clk_get_rate(clk->parent); in jz_clk_pll_get_rate()
225 return ((clk_get_rate(clk->parent) / n) * m) / pllno[od]; in jz_clk_pll_get_rate()
234 return jz_clk_pll_get_rate(clk->parent); in jz_clk_pll_half_get_rate()
235 return jz_clk_pll_get_rate(clk->parent) >> 1; in jz_clk_pll_half_get_rate()
242 unsigned long parent_rate = jz_clk_pll_get_rate(clk->parent); in jz_clk_main_round_rate()
269 return jz_clk_pll_get_rate(clk->parent) / jz_clk_main_divs[div]; in jz_clk_main_get_rate()
277 unsigned long parent_rate = jz_clk_pll_get_rate(clk->parent); in jz_clk_main_set_rate()
314 .parent = &jz_clk_ext.clk,
324 .parent = &jz_clk_pll,
337 .parent = &jz_clk_pll,
[all …]
/arch/arm/mach-imx/
Dclk.h13 struct clk *imx_clk_pllv1(const char *name, const char *parent,
16 struct clk *imx_clk_pllv2(const char *name, const char *parent,
39 struct clk *imx_clk_gate_exclusive(const char *name, const char *parent,
42 static inline struct clk *imx_clk_gate2(const char *name, const char *parent, in imx_clk_gate2() argument
45 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, in imx_clk_gate2()
50 const char *parent, void __iomem *reg, u8 shift, in imx_clk_gate2_shared() argument
53 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, in imx_clk_gate2_shared()
68 struct clk *imx_clk_fixup_divider(const char *name, const char *parent,
81 static inline struct clk *imx_clk_divider(const char *name, const char *parent, in imx_clk_divider() argument
84 return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT, in imx_clk_divider()
[all …]
/arch/avr32/mach-at32ap/
Dclock.c73 if (clk->parent) in __clk_enable()
74 __clk_enable(clk->parent); in __clk_enable()
104 if (clk->parent) in __clk_disable()
105 __clk_disable(clk->parent); in __clk_disable()
174 int clk_set_parent(struct clk *clk, struct clk *parent) in clk_set_parent() argument
186 ret = clk->set_parent(clk, parent); in clk_set_parent()
195 return !clk ? NULL : clk->parent; in clk_get_parent()
220 dump_clock(struct clk *parent, struct clkinf *r) in dump_clock() argument
228 if (parent->dev && !dev_name(parent->dev) && !parent->users) in dump_clock()
234 i = strlen(parent->name); in dump_clock()
[all …]
/arch/arm/mach-lpc32xx/
Dclock.c121 clk = clk->parent; in local_return_parent_rate()
191 .parent = &osc_32KHz,
262 clkin = clk_armpll.parent->rate; in local_update_armpll_rate()
368 .parent = &clk_sys,
383 return clk_check_pll_setup(clk_usbpll.parent->rate, in local_clk_usbpll_setup()
487 clkin = clk->get_rate(clk->parent); in local_usbpll_set_rate()
518 .parent = &osc_main,
534 .parent = &clk_armpll,
539 .parent = &clk_armpll,
561 .parent = &clk_pclk,
[all …]
/arch/blackfin/mach-bf609/
Dclock.c148 clk->parent->rate = clk_get_rate(clk->parent); in pll_get_rate()
149 return clk->parent->rate / (df + 1) * msel * 2; in pll_get_rate()
155 div = rate / clk->parent->rate; in pll_round_rate()
156 return clk->parent->rate * div; in pll_round_rate()
169 msel = rate / clk->parent->rate / 2; in pll_set_rate()
178 if (clk->parent) in cclk_get_rate()
179 return clk->parent->rate; in cclk_get_rate()
195 if (!strcmp(clk->parent->name, "SYS_CLKIN")) { in sys_clk_get_rate()
196 drate = clk->parent->rate / (df + 1); in sys_clk_get_rate()
201 clk->parent->rate = clk_get_rate(clk->parent); in sys_clk_get_rate()
[all …]
/arch/arm/mach-omap2/
Dclock36xx.c43 struct clk_divider *parent; in omap36xx_pwrdn_clk_enable_with_hsdiv_restore() local
53 parent = to_clk_divider(parent_hw); in omap36xx_pwrdn_clk_enable_with_hsdiv_restore()
57 orig_v = omap2_clk_readl(omap_clk, parent->reg); in omap36xx_pwrdn_clk_enable_with_hsdiv_restore()
61 dummy_v ^= (1 << parent->shift); in omap36xx_pwrdn_clk_enable_with_hsdiv_restore()
62 omap2_clk_writel(dummy_v, omap_clk, parent->reg); in omap36xx_pwrdn_clk_enable_with_hsdiv_restore()
65 omap2_clk_writel(orig_v, omap_clk, parent->reg); in omap36xx_pwrdn_clk_enable_with_hsdiv_restore()
Dclkt_clksel.c69 for (clks = clk->clksel; clks->parent; clks++) in _get_clksel_by_parent()
70 if (clks->parent == src_clk) in _get_clksel_by_parent()
73 if (!clks->parent) { in _get_clksel_by_parent()
123 struct clk *parent; in _clksel_to_divisor() local
125 parent = __clk_get_parent(clk->hw.clk); in _clksel_to_divisor()
127 clks = _get_clksel_by_parent(clk, parent); in _clksel_to_divisor()
143 __clk_get_name(parent)); in _clksel_to_divisor()
164 struct clk *parent; in _divisor_to_clksel() local
169 parent = __clk_get_parent(clk->hw.clk); in _divisor_to_clksel()
170 clks = _get_clksel_by_parent(clk, parent); in _divisor_to_clksel()
[all …]
/arch/arm/mach-ep93xx/
Dclock.c31 struct clk *parent; member
54 .parent = &clk_xtali,
61 .parent = &clk_xtali,
68 .parent = &clk_xtali,
75 .parent = &clk_xtali,
78 .parent = &clk_pll1,
81 .parent = &clk_pll1,
84 .parent = &clk_pll1,
87 .parent = &clk_xtali,
90 .parent = &clk_pll2,
[all …]
/arch/arm/mach-davinci/
Dclock.c36 if (clk->parent) in __clk_enable()
37 __clk_enable(clk->parent); in __clk_enable()
58 if (clk->parent) in __clk_disable()
59 __clk_disable(clk->parent); in __clk_disable()
180 int clk_set_parent(struct clk *clk, struct clk *parent) in clk_set_parent() argument
192 clk->parent = parent; in clk_set_parent()
194 list_add(&clk->childnode, &clk->parent->children); in clk_set_parent()
212 if (WARN(clk->parent && !clk->parent->rate, in clk_register()
214 clk->name, clk->parent->name)) in clk_register()
221 if (clk->parent) in clk_register()
[all …]
Ddm646x.c77 .parent = &ref_clk,
84 .parent = &pll1_clk,
91 .parent = &pll1_clk,
98 .parent = &pll1_clk,
105 .parent = &pll1_clk,
112 .parent = &pll1_clk,
119 .parent = &pll1_clk,
126 .parent = &pll1_clk,
133 .parent = &pll1_clk,
140 .parent = &pll1_clk,
[all …]
Ddm355.c65 .parent = &ref_clk,
72 .parent = &pll1_clk,
78 .parent = &pll1_clk,
85 .parent = &pll1_clk,
92 .parent = &pll1_clk,
99 .parent = &pll1_clk,
106 .parent = &pll1_clk,
113 .parent = &pll1_sysclk3,
119 .parent = &pll1_sysclk4,
126 .parent = &pll1_sysclk4,
[all …]
Ddm644x.c62 .parent = &ref_clk,
69 .parent = &pll1_clk,
76 .parent = &pll1_clk,
83 .parent = &pll1_clk,
90 .parent = &pll1_clk,
97 .parent = &pll1_clk,
103 .parent = &pll1_clk,
110 .parent = &ref_clk,
117 .parent = &pll2_clk,
124 .parent = &pll2_clk,
[all …]
Ddm365.c75 .parent = &ref_clk,
82 .parent = &pll1_clk,
88 .parent = &pll1_clk,
95 .parent = &pll1_clk,
101 .parent = &pll1_clk,
108 .parent = &pll1_clk,
115 .parent = &pll1_clk,
122 .parent = &pll1_clk,
129 .parent = &pll1_clk,
136 .parent = &pll1_clk,
[all …]
/arch/arm/mach-shmobile/
Dboard-ape6evm-reference.c37 struct clk *parent; in ape6evm_add_standard_devices() local
43 parent = clk_get(NULL, "extal2"); in ape6evm_add_standard_devices()
45 BUG_ON(IS_ERR(parent) || IS_ERR(mp)); in ape6evm_add_standard_devices()
47 clk_set_parent(mp, parent); in ape6evm_add_standard_devices()
48 clk_put(parent); in ape6evm_add_standard_devices()
/arch/parisc/kernel/
Dftrace.c109 void prepare_ftrace_return(unsigned long *parent, unsigned long self_addr) in prepare_ftrace_return() argument
121 old = *parent; in prepare_ftrace_return()
122 *parent = (unsigned long) in prepare_ftrace_return()
127 *parent = old; in prepare_ftrace_return()
136 *parent = old; in prepare_ftrace_return()
145 *parent = old; in prepare_ftrace_return()
152 void ftrace_function_trampoline(unsigned long parent, in ftrace_function_trampoline() argument
159 ftrace_trace_function(parent, self_addr); in ftrace_function_trampoline()
177 if (*parent_rp != parent) in ftrace_function_trampoline()
/arch/c6x/boot/dts/
Devmc6678.dts40 interrupt-parent = <&megamod_pic>;
45 interrupt-parent = <&megamod_pic>;
50 interrupt-parent = <&megamod_pic>;
55 interrupt-parent = <&megamod_pic>;
60 interrupt-parent = <&megamod_pic>;
65 interrupt-parent = <&megamod_pic>;
70 interrupt-parent = <&megamod_pic>;
75 interrupt-parent = <&megamod_pic>;
/arch/powerpc/kernel/
Deeh_pe.c155 if (next != &pe->parent->child_list) in eeh_pe_next()
157 pe = pe->parent; in eeh_pe_next()
287 struct eeh_dev *parent; in eeh_pe_get_parent() local
294 dn = edev->dn->parent; in eeh_pe_get_parent()
299 parent = of_node_to_eeh_dev(dn); in eeh_pe_get_parent()
301 if (!parent) return NULL; in eeh_pe_get_parent()
303 if (parent->pe) in eeh_pe_get_parent()
304 return parent->pe; in eeh_pe_get_parent()
306 dn = dn->parent; in eeh_pe_get_parent()
323 struct eeh_pe *pe, *parent; in eeh_add_to_parent_pe() local
[all …]
Disa-bridge.c131 struct device_node *np, *parent = NULL, *tmp; in isa_bridge_find_early() local
144 for (parent = of_get_parent(np); parent;) { in isa_bridge_find_early()
145 if (parent == hose->dn) { in isa_bridge_find_early()
146 of_node_put(parent); in isa_bridge_find_early()
149 tmp = parent; in isa_bridge_find_early()
150 parent = of_get_parent(parent); in isa_bridge_find_early()
153 if (parent != NULL) in isa_bridge_find_early()
/arch/arm/mach-omap1/
Dclock_data.c87 .parent = &ck_ref,
98 .parent = &ck_dpll1,
111 .parent = &ck_dpll1out.clk,
122 .parent = &ck_dpll1,
133 .parent = &ck_dpll1,
152 .parent = &ck_dpll1,
163 .parent = &ck_ref,
176 .parent = &ck_ref,
189 .parent = &ck_ref,
202 .parent = &arm_ck,
[all …]
/arch/arm/mach-at91/
Dclock.c133 .parent = &main_clk,
159 .parent = &main_clk,
192 .parent = &pllb,
197 .parent = &main_clk,
278 if (clk->parent) in __clk_enable()
279 __clk_enable(clk->parent); in __clk_enable()
300 if (clk->parent) in __clk_disable()
301 __clk_disable(clk->parent); in __clk_disable()
322 if (rate || !clk->parent) in clk_get_rate()
324 clk = clk->parent; in clk_get_rate()
[all …]
/arch/arm/boot/dts/
Dspear600.dtsi55 interrupt-parent = <&vic1>;
63 interrupt-parent = <&vic1>;
71 interrupt-parent = <&vic1>;
95 interrupt-parent = <&vic1>;
103 interrupt-parent = <&vic1>;
111 interrupt-parent = <&vic1>;
119 interrupt-parent = <&vic1>;
127 interrupt-parent = <&vic1>;
141 interrupt-parent = <&vic0>;
149 interrupt-parent = <&vic0>;
[all …]
/arch/powerpc/platforms/pseries/
Ddlpar.c130 struct device_node *parent) in dlpar_configure_connector() argument
139 const char *parent_path = parent->full_name; in dlpar_configure_connector()
177 dn->parent = last_dn->parent; in dlpar_configure_connector()
191 dn->parent = parent; in dlpar_configure_connector()
194 dn->parent = last_dn; in dlpar_configure_connector()
216 last_dn = last_dn->parent; in dlpar_configure_connector()
217 parent_path = last_dn->parent->full_name; in dlpar_configure_connector()
247 struct device_node *parent; in derive_parent() local
252 parent = of_find_node_by_path("/"); in derive_parent()
261 parent = of_find_node_by_path(parent_path); in derive_parent()
[all …]
/arch/microblaze/kernel/
Dftrace.c22 void prepare_ftrace_return(unsigned long *parent, unsigned long self_addr) in prepare_ftrace_return() argument
54 : "r" (parent), "r" (return_hooker) in prepare_ftrace_return()
57 flush_dcache_range((u32)parent, (u32)parent + 4); in prepare_ftrace_return()
58 flush_icache_range((u32)parent, (u32)parent + 4); in prepare_ftrace_return()
68 *parent = old; in prepare_ftrace_return()
76 *parent = old; in prepare_ftrace_return()

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