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Searched refs:pll0 (Results 1 – 20 of 20) sorted by relevance

/arch/powerpc/boot/dts/fsl/
Db4420si-post.dtsi95 pll0: pll0@800 { label
100 clock-output-names = "pll0", "pll0-div2", "pll0-div4";
115 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
117 clock-names = "pll0", "pll0-div2", "pll0-div4",
Dt1040si-post.dtsi298 pll0: pll0@800 { label
303 clock-output-names = "pll0", "pll0-div2", "pll0-div4";
318 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
320 clock-names = "pll0", "pll0-div2", "pll1-div4",
329 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
331 clock-names = "pll0", "pll0-div2", "pll1-div4",
340 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
342 clock-names = "pll0", "pll0-div2", "pll1-div4",
351 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
Dp5040si-post.dtsi314 pll0: pll0@800 { label
319 clock-output-names = "pll0", "pll0-div2";
334 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
335 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
343 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
344 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
352 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
353 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
361 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
362 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
Dp2041si-post.dtsi322 pll0: pll0@800 { label
327 clock-output-names = "pll0", "pll0-div2";
342 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
343 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
351 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
352 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
360 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
361 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
369 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
370 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
Db4860si-post.dtsi139 pll0: pll0@800 { label
144 clock-output-names = "pll0", "pll0-div2", "pll0-div4";
159 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
161 clock-names = "pll0", "pll0-div2", "pll0-div4",
Dp3041si-post.dtsi349 pll0: pll0@800 { label
354 clock-output-names = "pll0", "pll0-div2";
369 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
370 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
378 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
379 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
387 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
388 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
396 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
397 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
Dp4080si-post.dtsi369 pll0: pll0@800 { label
374 clock-output-names = "pll0", "pll0-div2";
405 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
406 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
414 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
415 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
423 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
424 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
432 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
433 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
Dt2081si-post.dtsi321 pll0: pll0@800 { label
326 clock-output-names = "pll0", "pll0-div2", "pll0-div4";
341 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
343 clock-names = "pll0", "pll0-div2", "pll1-div4",
352 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
354 clock-names = "pll0", "pll0-div2", "pll1-div4",
Dt4240si-post.dtsi384 pll0: pll0@800 { label
389 clock-output-names = "pll0", "pll0-div2", "pll0-div4";
428 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
431 clock-names = "pll0", "pll0-div2", "pll0-div4",
441 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
444 clock-names = "pll0", "pll0-div2", "pll0-div4",
Dp5020si-post.dtsi354 pll0: pll0@800 { label
359 clock-output-names = "pll0", "pll0-div2";
374 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
375 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
383 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
384 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
/arch/arm/boot/dts/
Dstih415-clock.dtsi38 clock-output-names = "clk-s-a0-pll0-hs",
39 "clk-s-a0-pll0-ls",
96 clock-output-names = "clk-s-a1-pll0-hs",
97 "clk-s-a1-pll0-ls",
153 clk_m_a0_pll0: clk-m-a0-pll0 {
159 clock-output-names = "clk-m-a0-pll0-phi0",
160 "clk-m-a0-pll0-phi1",
161 "clk-m-a0-pll0-phi2",
162 "clk-m-a0-pll0-phi3";
267 clk_m_a1_pll0: clk-m-a1-pll0 {
[all …]
Dstih416-clock.dtsi39 clock-output-names = "clk-s-a0-pll0-hs",
40 "clk-s-a0-pll0-ls",
97 clock-output-names = "clk-s-a1-pll0-hs",
98 "clk-s-a1-pll0-ls",
155 clk_m_a0_pll0: clk-m-a0-pll0 {
161 clock-output-names = "clk-m-a0-pll0-phi0",
162 "clk-m-a0-pll0-phi1",
163 "clk-m-a0-pll0-phi2",
164 "clk-m-a0-pll0-phi3";
269 clk_m_a1_pll0: clk-m-a1-pll0 {
[all …]
Ddove-cubox.dts91 /* connect xtal input as source of pll0 and pll1 */
Dr8a7794.dtsi285 clock-output-names = "main", "pll0", "pll1", "pll3",
Dr8a7790.dtsi656 clock-output-names = "main", "pll0", "pll1", "pll3",
Dr8a7791.dtsi693 clock-output-names = "main", "pll0", "pll1", "pll3",
/arch/arc/boot/dts/
Dabilis_tb10x.dtsi46 pll0: oscillator { label
49 clock-output-names = "pll0";
54 clocks = <&pll0>;
60 clocks = <&pll0>;
Dabilis_tb100.dtsi31 pll0: oscillator { label
Dabilis_tb101.dtsi31 pll0: oscillator { label
/arch/avr32/mach-at32ap/
Dat32ap700x.c311 static struct clk pll0 = { variable
574 else if (parent == &osc0 || parent == &pll0) in genclk_set_parent()
579 if (parent == &pll0 || parent == &pll1) in genclk_set_parent()
601 parent = (control & PM_BIT(PLLSEL)) ? &pll0 : &osc0; in genclk_init_parent()
1517 clk_set_parent(&atmel_lcdfb0_pixclk, &pll0); in at32_add_device_lcdc()
1518 clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0)); in at32_add_device_lcdc()
2207 &pll0,
2274 main_clock = &pll0; in setup_platform()
2275 cpu_clk.parent = &pll0; in setup_platform()
2282 pll0.parent = &osc1; in setup_platform()