Searched refs:pll0_clk (Results 1 – 4 of 4) sorted by relevance
| /arch/arm/mach-davinci/ |
| D | da850.c | 65 static struct clk pll0_clk = { variable
75 .parent = &pll0_clk,
81 .parent = &pll0_clk,
88 .parent = &pll0_clk,
95 .parent = &pll0_clk,
104 .parent = &pll0_clk,
111 .parent = &pll0_clk,
118 .parent = &pll0_clk,
125 .parent = &pll0_clk,
431 CLK(NULL, "pll0", &pll0_clk),
[all …]
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| D | da830.c | 51 static struct clk pll0_clk = { variable
60 .parent = &pll0_clk,
66 .parent = &pll0_clk,
73 .parent = &pll0_clk,
80 .parent = &pll0_clk,
87 .parent = &pll0_clk,
94 .parent = &pll0_clk,
101 .parent = &pll0_clk,
378 CLK(NULL, "pll0", &pll0_clk),
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| /arch/arm/mach-shmobile/ |
| D | clock-r8a73a4.c | 183 PLL_CLOCK(pll0_clk, &main_clk, pll_parent_main, 1, 20, PLL0CR, 0);
319 .parent = &pll0_clk,
331 SH_FIXED_RATIO_CLK(pll0_div2_clk, pll0_clk, div2);
353 &pll0_clk,
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| D | clock-sh73a0.c | 120 static struct clk pll0_clk = { variable
179 &pll0_clk,
236 [DIV4_ZG] = SH_CLK_DIV4(&pll0_clk, FRQCRA, 16, 0xd7f, CLK_ENABLE_ON_INIT),
241 [DIV4_Z] = SH_CLK_DIV4(&pll0_clk, FRQCRB, 24, 0x97f, 0),
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