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Searched refs:pm_readl (Results 1 – 3 of 3) sorted by relevance

/arch/avr32/mach-at32ap/
Dclock.c264 seq_printf(s, "MCCTRL = %8x\n", pm_readl(MCCTRL)); in clk_show()
265 seq_printf(s, "CKSEL = %8x\n", pm_readl(CKSEL)); in clk_show()
266 seq_printf(s, "CPUMASK = %8x\n", pm_readl(CPU_MASK)); in clk_show()
267 seq_printf(s, "HSBMASK = %8x\n", pm_readl(HSB_MASK)); in clk_show()
268 seq_printf(s, "PBAMASK = %8x\n", pm_readl(PBA_MASK)); in clk_show()
269 seq_printf(s, "PBBMASK = %8x\n", pm_readl(PBB_MASK)); in clk_show()
270 seq_printf(s, "PLL0 = %8x\n", pm_readl(PLL0)); in clk_show()
271 seq_printf(s, "PLL1 = %8x\n", pm_readl(PLL1)); in clk_show()
272 seq_printf(s, "IMR = %8x\n", pm_readl(IMR)); in clk_show()
276 seq_printf(s, "GCCTRL%d = %8x\n", i, pm_readl(GCCTRL(i))); in clk_show()
Dat32ap700x.c198 control = pm_readl(PLL0); in pll0_get_rate()
209 ctrl = pm_readl(PLL1); in pll1_mode()
223 status = pm_readl(ISR); in pll1_mode()
242 control = pm_readl(PLL1); in pll1_get_rate()
274 ctrl = pm_readl(PLL1); in pll1_set_parent()
349 mask = pm_readl(CPU_MASK); in cpu_clk_mode()
362 cksel = pm_readl(CKSEL); in cpu_clk_get_rate()
375 control = pm_readl(CKSEL); in cpu_clk_set_rate()
410 mask = pm_readl(HSB_MASK); in hsb_clk_mode()
423 cksel = pm_readl(CKSEL); in hsb_clk_get_rate()
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Dpm.h107 #define pm_readl(reg) \ macro