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Searched refs:postdiv (Results 1 – 6 of 6) sorted by relevance

/arch/mips/ar7/
Dclock.c85 u32 postdiv; member
112 int *postdiv, int *mul) in approximate() argument
123 *postdiv = k; in approximate()
128 static void calculate(int base, int target, int *prediv, int *postdiv, in calculate() argument
137 *postdiv = tmp_base / tmp_gcd; in calculate()
140 if ((*postdiv > 0) & (*postdiv <= 32)) in calculate()
144 if (base / *prediv * *mul / *postdiv != target) { in calculate()
145 approximate(base, target, prediv, postdiv, mul); in calculate()
146 tmp_freq = base / *prediv * *mul / *postdiv; in calculate()
153 *prediv, *postdiv, *mul); in calculate()
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/arch/mips/ath79/
Dclock.c243 u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv; in ar934x_clocks_init() local
312 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) & in ar934x_clocks_init()
318 cpu_rate = cpu_pll / (postdiv + 1); in ar934x_clocks_init()
320 cpu_rate = ddr_pll / (postdiv + 1); in ar934x_clocks_init()
322 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) & in ar934x_clocks_init()
328 ddr_rate = ddr_pll / (postdiv + 1); in ar934x_clocks_init()
330 ddr_rate = cpu_pll / (postdiv + 1); in ar934x_clocks_init()
332 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) & in ar934x_clocks_init()
338 ahb_rate = ddr_pll / (postdiv + 1); in ar934x_clocks_init()
340 ahb_rate = cpu_pll / (postdiv + 1); in ar934x_clocks_init()
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/arch/arm/mach-davinci/
Dclock.c410 u32 ctrl, mult = 1, prediv = 1, postdiv = 1; in clk_pllclk_recalc() local
441 postdiv = __raw_readl(pll->base + POSTDIV); in clk_pllclk_recalc()
442 if (postdiv & PLLDIV_EN) in clk_pllclk_recalc()
443 postdiv = (postdiv & pll->div_ratio_mask) + 1; in clk_pllclk_recalc()
445 postdiv = 1; in clk_pllclk_recalc()
451 rate /= postdiv; in clk_pllclk_recalc()
462 if (postdiv > 1) in clk_pllclk_recalc()
463 pr_debug("/ %d ", postdiv); in clk_pllclk_recalc()
480 unsigned int mult, unsigned int postdiv) in davinci_set_pllrate() argument
500 if (postdiv) in davinci_set_pllrate()
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Dda850.c947 unsigned int postdiv; member
956 .postdiv = 1,
965 .postdiv = 1,
974 .postdiv = 1,
983 .postdiv = 2,
992 .postdiv = 3,
1001 .postdiv = 5,
1125 unsigned int prediv, mult, postdiv; in da850_set_pll0rate() local
1133 postdiv = opp->postdiv; in da850_set_pll0rate()
1135 ret = davinci_set_pllrate(pll, prediv, mult, postdiv); in da850_set_pll0rate()
Dclock.h129 unsigned int mult, unsigned int postdiv);
/arch/c6x/platforms/
Dpll.c271 u32 ctrl, mult = 0, prediv = 0, postdiv = 0; in clk_pllclk_recalc() local
299 postdiv = pll_read(pll, PLLPOST); in clk_pllclk_recalc()
300 if (postdiv & PLLDIV_EN) in clk_pllclk_recalc()
301 postdiv = (postdiv & PLLDIV_RATIO_MASK) + 1; in clk_pllclk_recalc()
303 postdiv = 1; in clk_pllclk_recalc()
311 if (postdiv) in clk_pllclk_recalc()
312 rate /= postdiv; in clk_pllclk_recalc()
317 prediv, mult, postdiv, rate / 1000000); in clk_pllclk_recalc()