| /arch/powerpc/platforms/ps3/ |
| D | hvcall.S | 31 std r0, 16(r1); \
36 ld r0, 16(r1); \
53 std r0, 16(r1); \
55 stdu r3, -8(r1); \
60 addi r1, r1, 8; \
61 ld r11, -8(r1); \
64 ld r0, 16(r1); \
72 std r0, 16(r1); \
74 std r3, -8(r1); \
75 stdu r4, -16(r1); \
[all …]
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| /arch/microblaze/kernel/ |
| D | mcount.S | 18 addik r1, r1, -120; \
19 swi r2, r1, 4; \
20 swi r3, r1, 8; \
21 swi r4, r1, 12; \
22 swi r5, r1, 116; \
23 swi r6, r1, 16; \
24 swi r7, r1, 20; \
25 swi r8, r1, 24; \
26 swi r9, r1, 28; \
27 swi r10, r1, 32; \
[all …]
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| D | entry-nommu.S | 54 swi r1, r0, PER_CPU(ENTRY_SP) /* save the current sp */
60 addik r1, r1, (-PT_SIZE) /* room for pt_regs (delay slot) */
62 lwi r1, r0, PER_CPU(CURRENT_SAVE) /* get the saved current */
63 lwi r1, r1, TS_THREAD_INFO /* get the thread info */
65 addik r1, r1, THREAD_SIZE - PT_SIZE
67 swi r11, r1, PT_MODE /* store the mode */
69 swi r2, r1, PT_R2
70 swi r3, r1, PT_R3
71 swi r4, r1, PT_R4
72 swi r5, r1, PT_R5
[all …]
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| D | entry.S | 178 swi r2, r1, PT_R2; /* Save SDA */ \
179 swi r3, r1, PT_R3; \
180 swi r4, r1, PT_R4; \
181 swi r5, r1, PT_R5; \
182 swi r6, r1, PT_R6; \
183 swi r7, r1, PT_R7; \
184 swi r8, r1, PT_R8; \
185 swi r9, r1, PT_R9; \
186 swi r10, r1, PT_R10; \
187 swi r11, r1, PT_R11; /* save clobbered regs after rval */\
[all …]
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| /arch/tile/lib/ |
| D | usercopy_32.S | 30 { bz r1, 2f; or r2, r0, r1 }
33 1: { sb r0, zero; addi r0, r0, 1; addi r1, r1, -1 }
34 bnzt r1, 1b
35 2: { move r0, r1; jrp lr }
42 1: { sw r0, zero; addi r0, r0, 4; addi r1, r1, -4 }
43 bnzt r1, 1b
44 2: { move r0, r1; jrp lr }
57 bz r1, 2f
58 { movei r2, L2_CACHE_BYTES; add r1, r0, r1 }
59 { sub r2, zero, r2; addi r1, r1, L2_CACHE_BYTES-1 }
[all …]
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| D | usercopy_64.S | 30 { beqz r1, 2f; or r2, r0, r1 }
33 1: { st1 r0, zero; addi r0, r0, 1; addi r1, r1, -1 }
34 bnezt r1, 1b
35 2: { move r0, r1; jrp lr }
42 1: { st r0, zero; addi r0, r0, 8; addi r1, r1, -8 }
43 bnezt r1, 1b
44 2: { move r0, r1; jrp lr }
57 beqz r1, 2f
58 { movei r2, L2_CACHE_BYTES; add r1, r0, r1 }
59 { sub r2, zero, r2; addi r1, r1, L2_CACHE_BYTES-1 }
[all …]
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| D | memcpy_32.S | 91 { sw sp, lr; move r23, r0; or r4, r0, r1 }
97 { move r24, r1; move r25, r2 }
108 { andi r6, r1, 63; j .Lcopy_many }
118 EX: { lw r3, r1; addi r1, r1, 4; slti_u r8, r2, 16 }
119 EX: { lw r4, r1; addi r1, r1, 4 }
127 EX: { lw r3, r1; addi r1, r1, 4 }
146 EX: { lw r3, r1; addi r1, r1, 4 }
147 { andi r6, r1, 63 }
152 { addi r3, r1, 60; andi r9, r9, -64 }
182 { jal .Lcopy_line2; add r15, r1, r2 }
[all …]
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| /arch/powerpc/include/asm/ |
| D | ftrace.h | 13 stwu r1,-48(r1); \
14 stw r3, 12(r1); \
15 stw r4, 16(r1); \
16 stw r5, 20(r1); \
17 stw r6, 24(r1); \
19 lwz r4, 52(r1); \
21 stw r7, 28(r1); \
22 stw r8, 32(r1); \
23 stw r9, 36(r1); \
24 stw r10,40(r1); \
[all …]
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| /arch/arc/lib/ |
| D | strlen.S | 18 asl_s r1,r0,3
20 asl r7,r4,r1
22 sub r1,r2,r7
23 bic_s r1,r1,r2
27 or.eq r12,r12,r1
33 mov_s r1,31
34 sub3 r7,r1,r0
35 sub r1,r2,r4
36 bic_s r1,r1,r2
37 bmsk r1,r1,r7
[all …]
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| /arch/s390/kernel/ |
| D | swsusp_asm64.S | 29 lgr %r1,%r15
31 stg %r1,__SF_BACKCHAIN(%r15)
43 lghi %r1,0x1000
49 mvc 0x318(4,%r1),__SF_EMPTY(%r15) /* move prefix to lowcore */
50 stfpc 0x31c(%r1) /* store fpu control */
51 std 0,0x200(%r1) /* store f0 */
52 std 1,0x208(%r1) /* store f1 */
53 std 2,0x210(%r1) /* store f2 */
54 std 3,0x218(%r1) /* store f3 */
55 std 4,0x220(%r1) /* store f4 */
[all …]
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| D | base.S | 20 larl %r1,s390_base_mcck_handler_fn
21 lg %r1,0(%r1)
22 ltgr %r1,%r1
24 basr %r14,%r1
25 1: la %r1,4095
26 lmg %r0,%r15,__LC_GPREGS_SAVE_AREA-4095(%r1)
40 larl %r1,s390_base_ext_handler_fn
41 lg %r1,0(%r1)
42 ltgr %r1,%r1
44 basr %r14,%r1
[all …]
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| /arch/blackfin/mach-bf561/ |
| D | atomic.S | 41 r1 = -L1_CACHE_BYTES; define
42 r1 = r0 & r1; define
51 p0 = r1;
95 r1 = 0; define
96 [p0] = r1;
203 p1 = r1;
210 r1 = 1; define
211 r1 <<= r2;
212 r2 = ~r1;
214 r1 = [p1]; define
[all …]
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| /arch/powerpc/kernel/ |
| D | entry_64.S | 57 mr r10,r1
58 addi r1,r1,-INT_FRAME_SIZE
60 ld r1,PACAKSAVE(r13)
61 1: std r10,0(r1)
62 std r11,_NIP(r1)
63 std r12,_MSR(r1)
64 std r0,GPR0(r1)
65 std r10,GPR1(r1)
68 2: std r2,GPR2(r1)
69 std r3,GPR3(r1)
[all …]
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| D | entry_32.S | 99 rlwimi r0,r1,0,0,(31-THREAD_SHIFT)
123 rlwimi r0,r1,0,0,(31-THREAD_SHIFT)
154 addi r11,r1,STACK_FRAME_OVERHEAD
169 CURRENT_THREAD_INFO(r9, r1)
186 cmplw r1,r9 /* if r1 <= ksp_limit */
190 CURRENT_THREAD_INFO(r9, r1)
212 lwz r12,_MSR(r1)
231 stwu r1,-32(r1)
232 stw r9,8(r1)
233 stw r11,12(r1)
[all …]
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| D | idle_power7.S | 28 std r0,0(r1); \
30 ld r0,0(r1); \
56 std r0,16(r1)
57 stdu r1,-INT_FRAME_SIZE(r1)
58 std r0,_LINK(r1)
59 std r0,_NIP(r1)
80 addi r1,r1,INT_FRAME_SIZE
81 ld r0,16(r1)
97 SAVE_GPR(2, r1)
98 SAVE_NVGPRS(r1)
[all …]
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| /arch/hexagon/kernel/ |
| D | head.S | 53 r1.h = #HI(PAGE_OFFSET);
54 r1.l = #LO(PAGE_OFFSET);
55 r24 = sub(r24,r1); /* swapper_pg_dir - PAGE_OFFSET */
75 r1.l = #LO(_end);
80 r1.h = #HI(_end);
85 r1 = sub(r1, r2); define
88 r1 = add(r1, r3); /* + (4M-1) */ define
89 r26 = lsr(r1, #22); /* / 4M = # of entries */
91 r1 = r25; define
94 r1 = and(r1,r2); define
[all …]
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| /arch/arm/lib/ |
| D | memset.S | 25 1: orr r1, r1, r1, lsl #8
26 orr r1, r1, r1, lsl #16
27 mov r3, r1
37 mov r8, r1
38 mov lr, r1
41 stmgeia ip!, {r1, r3, r8, lr} @ 64 bytes at a time.
42 stmgeia ip!, {r1, r3, r8, lr}
43 stmgeia ip!, {r1, r3, r8, lr}
44 stmgeia ip!, {r1, r3, r8, lr}
51 stmneia ip!, {r1, r3, r8, lr}
[all …]
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| /arch/sh/lib/ |
| D | strlen.S | 25 mov.b @r4+,r1
26 tst r1,r1
30 mov.b @r4+,r1
31 tst r1,r1
35 mov.b @r4+,r1
36 tst r1,r1
43 mov.l @r4+,r1
44 cmp/str r3,r1
50 swap.b r1,r1
51 swap.w r1,r1
[all …]
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| /arch/arm/mach-tegra/ |
| D | sleep-tegra30.S | 187 str r12, [r1]
195 ldr r3, [r1] @ read CSR
196 str r3, [r1] @ clear CSR
265 mov32 r1, tegra30_iram_start
266 sub r0, r0, r1
267 mov32 r1, TEGRA_IRAM_LPx_RESUME_AREA
268 add r0, r0, r1
329 mov r1, #(1 << 28)
330 str r1, [r0, #CLK_RESET_SCLK_BURST]
331 str r1, [r0, #CLK_RESET_CCLK_BURST]
[all …]
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| /arch/openrisc/kernel/ |
| D | entry.S | 54 l.lwz r3,PT_PC(r1) ;\
56 l.lwz r3,PT_SR(r1) ;\
58 l.lwz r2,PT_GPR2(r1) ;\
59 l.lwz r3,PT_GPR3(r1) ;\
60 l.lwz r4,PT_GPR4(r1) ;\
61 l.lwz r5,PT_GPR5(r1) ;\
62 l.lwz r6,PT_GPR6(r1) ;\
63 l.lwz r7,PT_GPR7(r1) ;\
64 l.lwz r8,PT_GPR8(r1) ;\
65 l.lwz r9,PT_GPR9(r1) ;\
[all …]
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| /arch/m32r/lib/ |
| D | memset.S | 35 stb r1, @r4 || addi r4, #1
41 and3 r1, r1, #0x00ff /* r1: abababab <-- ??????ab */
42 sll3 r3, r1, #8
43 or r1, r3 || addi r4, #-4
44 sll3 r3, r1, #16
45 or r1, r3 || addi r2, #-4
47 st r1, @+r4 || addi r2, #-4
50 st r1, @+r4
57 and3 r1, r1, #0x00ff /* r1: abababab <-- ??????ab */
58 sll3 r3, r1, #8
[all …]
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| /arch/m32r/mm/ |
| D | mmu.S | 31 st r1, @-sp
36 ld r1, @(MESTS_offset, r3) ; r1: status (MESTS reg.)
38 st r1, @(MESTS_offset, r3) ; clear status (MESTS reg.)
39 and3 r1, r1, #(MESTS_IT)
40 bnez r1, 1f ; instruction TLB miss?
45 ;; r1 - r3: free
48 ;; r1: TLB entry base address
56 ldi r1, #-8192
59 and r1, sp
60 ld r1, @(16, r1) ; current_thread_info->cpu
[all …]
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| /arch/powerpc/platforms/powermac/ |
| D | sleep.S | 62 stw r0,4(r1)
63 stwu r1,-SL_SIZE(r1)
65 stw r0,SL_CR(r1)
66 stw r2,SL_R2(r1)
67 stmw r12,SL_R12(r1)
71 stw r4,SL_MSR(r1)
73 stw r4,SL_SDR1(r1)
77 stw r4,SL_TB(r1)
79 stw r5,SL_TB+4(r1)
86 stw r4,SL_SPRG0(r1)
[all …]
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| /arch/powerpc/platforms/pseries/ |
| D | hvCall.S | 37 std r3,STK_PARAM(R3)(r1); \
38 std r4,STK_PARAM(R4)(r1); \
39 std r5,STK_PARAM(R5)(r1); \
40 std r6,STK_PARAM(R6)(r1); \
41 std r7,STK_PARAM(R7)(r1); \
42 std r8,STK_PARAM(R8)(r1); \
43 std r9,STK_PARAM(R9)(r1); \
44 std r10,STK_PARAM(R10)(r1); \
45 std r0,16(r1); \
46 addi r4,r1,STK_PARAM(FIRST_REG); \
[all …]
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| /arch/unicore32/kernel/ |
| D | debug.S | 30 mov r1, #8
35 mov r1, #4
40 mov r1, #2
42 add r3, r2, r1
43 mov r1, #0
44 stb r1, [r3]
45 1: and r1, r0, #15
47 csub.a r1, #10
49 add r1, r1, #'0' - 'a' + 10
50 2: add r1, r1, #'a' - 10
[all …]
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