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Searched refs:rates (Results 1 – 8 of 8) sorted by relevance

/arch/mips/lantiq/
Dclk.c86 if (clk->rates && *clk->rates) { in clk_set_rate()
87 unsigned long *r = clk->rates; in clk_set_rate()
Dclk.h58 unsigned long *rates; member
/arch/arm/mach-omap2/
Dclkt_clksel.c131 for (clkr = clks->rates; clkr->div; clkr++) { in _clksel_to_divisor()
174 for (clkr = clks->rates; clkr->div; clkr++) { in _divisor_to_clksel()
256 for (clkr = clks->rates; clkr->div; clkr++) { in omap2_clksel_round_rate_div()
327 for (clkr = clks->rates; clkr->div && !found; clkr++) { in omap2_clksel_find_parent_index()
Dcclock3xxx_data.c607 { .parent = &core_ck, .rates = clkout2_src_core_rates },
608 { .parent = &sys_ck, .rates = clkout2_src_sys_rates },
609 { .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates },
610 { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates },
645 { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
646 { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
1209 { .parent = &sys_ck, .rates = emu_src_sys_rates },
1210 { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
1211 { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates },
1212 { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates },
[all …]
Dclock.h153 const struct clksel_rate *rates; member
/arch/mips/lantiq/xway/
Dsysctrl.c189 if (clk->rates[i] == clk->rate) { in clkout_enable()
248 clk->rates = valid_pci_rates; in clkdev_add_pci()
288 clk->rates = valid_clkout_rates[i]; in clkdev_add_clkout()
/arch/arm/boot/dts/
Dqcom-ipq8064.dtsi263 assigned-clock-rates = <100000000>, <100000000>;
Dste-nomadik-stn8815.dtsi235 /* PLL2 is usually 864 MHz and divided into a few fixed rates */