Home
last modified time | relevance | path

Searched refs:reg (Results 1 – 25 of 1988) sorted by relevance

12345678910>>...80

/arch/mips/include/asm/
Dasm-eva.h18 #define kernel_ll(reg, addr) "ll " reg ", " addr "\n" argument
19 #define kernel_sc(reg, addr) "sc " reg ", " addr "\n" argument
20 #define kernel_lw(reg, addr) "lw " reg ", " addr "\n" argument
21 #define kernel_lwl(reg, addr) "lwl " reg ", " addr "\n" argument
22 #define kernel_lwr(reg, addr) "lwr " reg ", " addr "\n" argument
23 #define kernel_lh(reg, addr) "lh " reg ", " addr "\n" argument
24 #define kernel_lb(reg, addr) "lb " reg ", " addr "\n" argument
25 #define kernel_lbu(reg, addr) "lbu " reg ", " addr "\n" argument
26 #define kernel_sw(reg, addr) "sw " reg ", " addr "\n" argument
27 #define kernel_swl(reg, addr) "swl " reg ", " addr "\n" argument
[all …]
/arch/parisc/include/asm/
Dasmregs.h24 rp: .reg %r2
25 arg3: .reg %r23
26 arg2: .reg %r24
27 arg1: .reg %r25
28 arg0: .reg %r26
29 dp: .reg %r27
30 ret0: .reg %r28
31 ret1: .reg %r29
32 sl: .reg %r29
33 sp: .reg %r30
[all …]
/arch/m32r/kernel/
Dentry.S83 #define R4(reg) @reg argument
84 #define R5(reg) @(0x04,reg) argument
85 #define R6(reg) @(0x08,reg) argument
86 #define PTREGS(reg) @(0x0C,reg) argument
87 #define R0(reg) @(0x10,reg) argument
88 #define R1(reg) @(0x14,reg) argument
89 #define R2(reg) @(0x18,reg) argument
90 #define R3(reg) @(0x1C,reg) argument
91 #define R7(reg) @(0x20,reg) argument
92 #define R8(reg) @(0x24,reg) argument
[all …]
/arch/ia64/include/asm/native/
Dpvchk_inst.h127 .macro is_rreg_in reg
133 mov \reg = r0
136 #define IS_RREG_IN(reg) is_rreg_in reg ; argument
138 #define IS_RREG_OUT(reg) \ argument
140 mov reg = r0 \
143 #define IS_RREG_CLOB(reg) IS_RREG_OUT(reg) argument
161 #define MOV_FROM_IFA(reg) \ argument
162 IS_RREG_OUT(reg)
163 #define MOV_FROM_ITIR(reg) \ argument
164 IS_RREG_OUT(reg)
[all …]
Dinst.h51 #define MOV_FROM_IFA(reg) \ argument
52 mov reg = cr.ifa
54 #define MOV_FROM_ITIR(reg) \ argument
55 mov reg = cr.itir
57 #define MOV_FROM_ISR(reg) \ argument
58 mov reg = cr.isr
60 #define MOV_FROM_IHA(reg) \ argument
61 mov reg = cr.iha
63 #define MOV_FROM_IPSR(pred, reg) \ argument
64 (pred) mov reg = cr.ipsr
[all …]
/arch/mips/include/asm/octeon/
Dcvmx-fau.h119 static inline uint64_t __cvmx_fau_store_address(uint64_t noadd, uint64_t reg) in __cvmx_fau_store_address() argument
123 cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg); in __cvmx_fau_store_address()
142 static inline uint64_t __cvmx_fau_atomic_address(uint64_t tagwait, uint64_t reg, in __cvmx_fau_atomic_address() argument
148 cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg); in __cvmx_fau_atomic_address()
160 static inline int64_t cvmx_fau_fetch_and_add64(cvmx_fau_reg_64_t reg, in cvmx_fau_fetch_and_add64() argument
163 return cvmx_read64_int64(__cvmx_fau_atomic_address(0, reg, value)); in cvmx_fau_fetch_and_add64()
175 static inline int32_t cvmx_fau_fetch_and_add32(cvmx_fau_reg_32_t reg, in cvmx_fau_fetch_and_add32() argument
178 return cvmx_read64_int32(__cvmx_fau_atomic_address(0, reg, value)); in cvmx_fau_fetch_and_add32()
189 static inline int16_t cvmx_fau_fetch_and_add16(cvmx_fau_reg_16_t reg, in cvmx_fau_fetch_and_add16() argument
192 return cvmx_read64_int16(__cvmx_fau_atomic_address(0, reg, value)); in cvmx_fau_fetch_and_add16()
[all …]
/arch/powerpc/platforms/cell/
Dcelleb_scc_epci.c72 PCI_IO_ADDR reg; in clear_and_disable_master_abort_interrupt() local
74 reg = epci_base + PCI_COMMAND; in clear_and_disable_master_abort_interrupt()
75 out_be32(reg, in_be32(reg) | (PCI_STATUS_REC_MASTER_ABORT << 16)); in clear_and_disable_master_abort_interrupt()
81 PCI_IO_ADDR reg; in celleb_epci_check_abort() local
88 reg = epci_base + PCI_COMMAND; in celleb_epci_check_abort()
89 val = in_be32(reg); in celleb_epci_check_abort()
92 out_be32(reg, in celleb_epci_check_abort()
96 reg = epci_base + SCC_EPCI_STATUS; in celleb_epci_check_abort()
97 out_be32(reg, SCC_EPCI_INT_PAI); in celleb_epci_check_abort()
99 reg = epci_base + SCC_EPCI_VCSR; in celleb_epci_check_abort()
[all …]
/arch/cris/include/arch-v32/arch/hwregs/
Dirq_nmi_defs.h18 #define REG_RD( scope, inst, reg ) \ argument
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \ argument
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \ argument
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
[all …]
Dstrcop_defs.h18 #define REG_RD( scope, inst, reg ) \ argument
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \ argument
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \ argument
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
[all …]
Dmarb_defs.h18 #define REG_RD( scope, inst, reg ) \ argument
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \ argument
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \ argument
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
[all …]
Dconfig_defs.h18 #define REG_RD( scope, inst, reg ) \ argument
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \ argument
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \ argument
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
[all …]
/arch/cris/include/arch-v32/arch/hwregs/iop/
Diop_version_defs.h18 #define REG_RD( scope, inst, reg ) \ argument
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \ argument
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \ argument
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
[all …]
Diop_scrc_out_defs.h18 #define REG_RD( scope, inst, reg ) \ argument
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \ argument
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \ argument
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
[all …]
Diop_scrc_in_defs.h18 #define REG_RD( scope, inst, reg ) \ argument
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \ argument
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \ argument
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
[all …]
/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/
Diop_version_defs.h15 #define REG_RD( scope, inst, reg ) \ argument
16 REG_READ( reg_##scope##_##reg, \
17 (inst) + REG_RD_ADDR_##scope##_##reg )
21 #define REG_WR( scope, inst, reg, val ) \ argument
22 REG_WRITE( reg_##scope##_##reg, \
23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27 #define REG_RD_VECT( scope, inst, reg, index ) \ argument
28 REG_READ( reg_##scope##_##reg, \
29 (inst) + REG_RD_ADDR_##scope##_##reg + \
30 (index) * STRIDE_##scope##_##reg )
[all …]
Diop_sap_in_defs.h15 #define REG_RD( scope, inst, reg ) \ argument
16 REG_READ( reg_##scope##_##reg, \
17 (inst) + REG_RD_ADDR_##scope##_##reg )
21 #define REG_WR( scope, inst, reg, val ) \ argument
22 REG_WRITE( reg_##scope##_##reg, \
23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27 #define REG_RD_VECT( scope, inst, reg, index ) \ argument
28 REG_READ( reg_##scope##_##reg, \
29 (inst) + REG_RD_ADDR_##scope##_##reg + \
30 (index) * STRIDE_##scope##_##reg )
[all …]
/arch/sh/include/mach-common/mach/
Dmagicpanelr2.h22 #define SETBITS_OUTB(mask, reg) __raw_writeb(__raw_readb(reg) | mask, reg) argument
23 #define SETBITS_OUTW(mask, reg) __raw_writew(__raw_readw(reg) | mask, reg) argument
24 #define SETBITS_OUTL(mask, reg) __raw_writel(__raw_readl(reg) | mask, reg) argument
25 #define CLRBITS_OUTB(mask, reg) __raw_writeb(__raw_readb(reg) & ~mask, reg) argument
26 #define CLRBITS_OUTW(mask, reg) __raw_writew(__raw_readw(reg) & ~mask, reg) argument
27 #define CLRBITS_OUTL(mask, reg) __raw_writel(__raw_readl(reg) & ~mask, reg) argument
/arch/blackfin/kernel/
Dpseudodbg.c23 static const char *get_allreg_name(int grp, int reg) in get_allreg_name() argument
25 return greg_names[(grp << 3) | reg]; in get_allreg_name()
40 static bool fix_up_reg(struct pt_regs *fp, long *value, int grp, int reg) in fix_up_reg() argument
47 (grp == 4 && (reg == 4 || reg == 5)) || in fix_up_reg()
51 if (grp == 0 || (grp == 1 && reg < 6)) in fix_up_reg()
52 val -= (reg + 8 * grp); in fix_up_reg()
53 else if (grp == 1 && reg == 6) in fix_up_reg()
55 else if (grp == 1 && reg == 7) in fix_up_reg()
59 val -= reg; in fix_up_reg()
60 } else if (grp == 3 && reg >= 4) { in fix_up_reg()
[all …]
/arch/arm/mach-tegra/
Dflowctrl.c76 unsigned int reg; in flowctrl_cpu_suspend_enter() local
79 reg = flowctrl_read_cpu_csr(cpuid); in flowctrl_cpu_suspend_enter()
83 reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP; in flowctrl_cpu_suspend_enter()
85 reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP; in flowctrl_cpu_suspend_enter()
87 reg |= TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 << cpuid; in flowctrl_cpu_suspend_enter()
93 reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP; in flowctrl_cpu_suspend_enter()
95 reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP; in flowctrl_cpu_suspend_enter()
97 reg |= TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 << cpuid; in flowctrl_cpu_suspend_enter()
100 reg |= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr flag */ in flowctrl_cpu_suspend_enter()
101 reg |= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event flag */ in flowctrl_cpu_suspend_enter()
[all …]
/arch/cris/include/arch-v32/mach-a3/mach/hwregs/
Dstrmux_defs.h15 #define REG_RD( scope, inst, reg ) \ argument
16 REG_READ( reg_##scope##_##reg, \
17 (inst) + REG_RD_ADDR_##scope##_##reg )
21 #define REG_WR( scope, inst, reg, val ) \ argument
22 REG_WRITE( reg_##scope##_##reg, \
23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27 #define REG_RD_VECT( scope, inst, reg, index ) \ argument
28 REG_READ( reg_##scope##_##reg, \
29 (inst) + REG_RD_ADDR_##scope##_##reg + \
30 (index) * STRIDE_##scope##_##reg )
[all …]
Dmarb_bar_defs.h15 #define REG_RD( scope, inst, reg ) \ argument
16 REG_READ( reg_##scope##_##reg, \
17 (inst) + REG_RD_ADDR_##scope##_##reg )
21 #define REG_WR( scope, inst, reg, val ) \ argument
22 REG_WRITE( reg_##scope##_##reg, \
23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27 #define REG_RD_VECT( scope, inst, reg, index ) \ argument
28 REG_READ( reg_##scope##_##reg, \
29 (inst) + REG_RD_ADDR_##scope##_##reg + \
30 (index) * STRIDE_##scope##_##reg )
[all …]
/arch/cris/include/arch-v32/mach-fs/mach/hwregs/
Dstrmux_defs.h18 #define REG_RD( scope, inst, reg ) \ argument
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \ argument
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \ argument
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
[all …]
Dmarb_defs.h18 #define REG_RD( scope, inst, reg ) \ argument
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \ argument
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \ argument
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
[all …]
/arch/x86/include/asm/
Dxor_avx.h43 #define BLOCK(i, reg) \ in xor_avx_2() argument
45 asm volatile("vmovdqa %0, %%ymm" #reg : : "m" (p1[i / sizeof(*p1)])); \ in xor_avx_2()
46 asm volatile("vxorps %0, %%ymm" #reg ", %%ymm" #reg : : \ in xor_avx_2()
48 asm volatile("vmovdqa %%ymm" #reg ", %0" : \ in xor_avx_2()
70 #define BLOCK(i, reg) \ in xor_avx_3() argument
72 asm volatile("vmovdqa %0, %%ymm" #reg : : "m" (p2[i / sizeof(*p2)])); \ in xor_avx_3()
73 asm volatile("vxorps %0, %%ymm" #reg ", %%ymm" #reg : : \ in xor_avx_3()
75 asm volatile("vxorps %0, %%ymm" #reg ", %%ymm" #reg : : \ in xor_avx_3()
77 asm volatile("vmovdqa %%ymm" #reg ", %0" : \ in xor_avx_3()
100 #define BLOCK(i, reg) \ in xor_avx_4() argument
[all …]
/arch/arm/mach-cns3xxx/
Dpm.c20 u32 reg = __raw_readl(PM_CLK_GATE_REG); in cns3xxx_pwr_clk_en() local
22 reg |= (block & PM_CLK_GATE_REG_MASK); in cns3xxx_pwr_clk_en()
23 __raw_writel(reg, PM_CLK_GATE_REG); in cns3xxx_pwr_clk_en()
29 u32 reg = __raw_readl(PM_CLK_GATE_REG); in cns3xxx_pwr_clk_dis() local
31 reg &= ~(block & PM_CLK_GATE_REG_MASK); in cns3xxx_pwr_clk_dis()
32 __raw_writel(reg, PM_CLK_GATE_REG); in cns3xxx_pwr_clk_dis()
38 u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG); in cns3xxx_pwr_power_up() local
40 reg &= ~(block & CNS3XXX_PWR_PLL_ALL); in cns3xxx_pwr_power_up()
41 __raw_writel(reg, PM_PLL_HM_PD_CTRL_REG); in cns3xxx_pwr_power_up()
50 u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG); in cns3xxx_pwr_power_down() local
[all …]

12345678910>>...80