| /arch/sh/drivers/pci/ |
| D | pci-sh7780.c | 103 addr = __raw_readl(hose->reg_base + SH4_PCIALR); in sh7780_pci_err_irq()
108 status = __raw_readw(hose->reg_base + PCI_STATUS); in sh7780_pci_err_irq()
116 __raw_writew(cmd, hose->reg_base + PCI_STATUS); in sh7780_pci_err_irq()
122 status = __raw_readl(hose->reg_base + SH4_PCIAINT); in sh7780_pci_err_irq()
130 __raw_writel(cmd, hose->reg_base + SH4_PCIAINT); in sh7780_pci_err_irq()
135 status = __raw_readl(hose->reg_base + SH4_PCIINT); in sh7780_pci_err_irq()
143 __raw_writel(cmd, hose->reg_base + SH4_PCIINT); in sh7780_pci_err_irq()
157 __raw_writel(SH4_PCIINTM_SDIM, hose->reg_base + SH4_PCIINTM); in sh7780_pci_serr_irq()
172 __raw_writel(0, hose->reg_base + SH4_PCIAINT); in sh7780_pci_setup_irqs()
180 PCI_STATUS_PARITY, hose->reg_base + PCI_STATUS); in sh7780_pci_setup_irqs()
[all …]
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| D | pci-sh4.h | 180 __raw_writel(val, chan->reg_base + reg); in pci_write_reg()
186 return __raw_readl(chan->reg_base + reg); in pci_read_reg()
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| D | pcie-sh7786.h | 571 __raw_writel(val, chan->reg_base + reg); in pci_write_reg()
577 return __raw_readl(chan->reg_base + reg); in pci_read_reg()
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| D | pci-sh7751.c | 86 chan->reg_base = 0xfe200000; in sh7751_pci_init()
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| D | pcie-sh7786.c | 120 .reg_base = start, \
239 clk->enable_reg = (void __iomem *)(chan->reg_base + SH4A_PCIEPHYCTLR); in pcie_clk_init()
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| /arch/powerpc/boot/ |
| D | uartlite.c | 29 static void * reg_base; variable
34 out_be32(reg_base + ULITE_CONTROL, ULITE_CONTROL_RST_RX); in uartlite_open()
42 reg = in_be32(reg_base + ULITE_STATUS); in uartlite_putc()
43 out_be32(reg_base + ULITE_TX, c); in uartlite_putc()
50 reg = in_be32(reg_base + ULITE_STATUS); in uartlite_getc()
51 return in_be32(reg_base + ULITE_RX); in uartlite_getc()
56 u32 reg = in_be32(reg_base + ULITE_STATUS); in uartlite_tstc()
65 n = getprop(devp, "virtual-reg", ®_base, sizeof(reg_base)); in uartlite_console_init()
66 if (n != sizeof(reg_base)) { in uartlite_console_init()
70 reg_base = (void *)reg_phys; in uartlite_console_init()
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| D | ns16550.c | 29 static unsigned char *reg_base; variable
34 out_8(reg_base + (UART_FCR << reg_shift), 0x06); in ns16550_open()
40 while ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_THRE) == 0); in ns16550_putc()
41 out_8(reg_base, c); in ns16550_putc()
46 while ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_DR) == 0); in ns16550_getc()
47 return in_8(reg_base); in ns16550_getc()
52 return ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_DR) != 0); in ns16550_tstc()
60 if (dt_get_virtual_reg(devp, (void **)®_base, 1) < 1) in ns16550_console_init()
65 reg_base += reg_offset; in ns16550_console_init()
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| D | virtex.c | 30 unsigned char *reg_base; in virtex_ns16550_console_init() local
35 if (dt_get_virtual_reg(devp, (void **)®_base, 1) < 1) in virtex_ns16550_console_init()
40 reg_base += reg_offset; in virtex_ns16550_console_init()
58 out_8(reg_base + (UART_LCR << reg_shift), UART_LCR_DLAB); in virtex_ns16550_console_init()
61 out_8(reg_base + (UART_DLL << reg_shift), divisor & 0xFF); in virtex_ns16550_console_init()
62 out_8(reg_base + (UART_DLM << reg_shift), divisor >> 8); in virtex_ns16550_console_init()
65 out_8(reg_base + (UART_LCR << reg_shift), UART_LCR_WLEN8); in virtex_ns16550_console_init()
68 out_8(reg_base + (UART_MCR << reg_shift), UART_MCR_RTS | UART_MCR_DTR); in virtex_ns16550_console_init()
71 out_8(reg_base + (UART_FCR << reg_shift), in virtex_ns16550_console_init()
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| /arch/sparc/kernel/ |
| D | sbus.c | 211 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL; in sbus_build_irq() local
221 imap += reg_base; in sbus_build_irq()
236 iclr = reg_base + SYSIO_ICLR_SLOT0; in sbus_build_irq()
239 iclr = reg_base + SYSIO_ICLR_SLOT1; in sbus_build_irq()
242 iclr = reg_base + SYSIO_ICLR_SLOT2; in sbus_build_irq()
246 iclr = reg_base + SYSIO_ICLR_SLOT3; in sbus_build_irq()
273 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL; in sysio_ue_handler() local
278 afsr_reg = reg_base + SYSIO_UE_AFSR; in sysio_ue_handler()
279 afar_reg = reg_base + SYSIO_UE_AFAR; in sysio_ue_handler()
347 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL; in sysio_ce_handler() local
[all …]
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| D | prom_irqtrans.c | 651 unsigned long reg_base = (unsigned long) _data; in sbus_of_build_irq() local
672 imap += reg_base; in sbus_of_build_irq()
685 iclr = reg_base + SYSIO_ICLR_SLOT0; in sbus_of_build_irq()
688 iclr = reg_base + SYSIO_ICLR_SLOT1; in sbus_of_build_irq()
691 iclr = reg_base + SYSIO_ICLR_SLOT2; in sbus_of_build_irq()
695 iclr = reg_base + SYSIO_ICLR_SLOT3; in sbus_of_build_irq()
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| /arch/arm/mach-s3c24xx/ |
| D | common.h | 117 void __iomem *reg_base);
121 unsigned long ext_f, void __iomem *reg_base);
126 void __iomem *reg_base);
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| /arch/mips/jz4740/ |
| D | irq.c | 58 writel(mask, gc->reg_base + regs->enable); in jz4740_irq_set_mask()
59 writel(~mask, gc->reg_base + regs->disable); in jz4740_irq_set_mask()
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| /arch/arm/mach-s3c64xx/ |
| D | common.h | 28 unsigned long xusbxti_f, bool is_s3c6400, void __iomem *reg_base);
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| /arch/sh/include/asm/ |
| D | pci.h | 28 unsigned long reg_base; member
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| /arch/powerpc/kvm/ |
| D | mpic.c | 198 gpa_t reg_base; member
1394 ret = kvm_mpic_read_internal(opp, addr - opp->reg_base, &u.val); in kvm_mpic_read()
1434 ret = kvm_mpic_write_internal(opp, addr - opp->reg_base, in kvm_mpic_write()
1454 opp->reg_base, OPENPIC_REG_SIZE, in map_mmio()
1476 if (base == opp->reg_base) in set_base_addr()
1482 opp->reg_base = base; in set_base_addr()
1572 attr64 = opp->reg_base; in mpic_get_attr()
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