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Searched refs:t5 (Results 1 – 25 of 27) sorted by relevance

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/arch/alpha/lib/
Dev67-strrchr.S36 insbl a1, 2, t5 # U : 0000000000ch0000
41 sll t5, 8, t3 # U : 00000000ch000000
45 or t5, t3, t3 # E : 00000000chch0000
52 lda t5, -1 # E : build garbage mask
55 mskqh t5, a0, t4 # E : Complete garbage mask
85 subq t4, 1, t5 # E : build a mask of the bytes up to...
86 or t4, t5, t4 # E : ... and including the null
101 lda t5, 0x3f($31) # E :
102 subq t5, t2, t5 # E : Normalize leading zero count
104 addq t6, t5, v0 # E : and add to quadword address
Dstrrchr.S23 sll a1, 8, t5 # e0 : replicate our test character
25 or t5, a1, a1 # e0 :
27 sll a1, 16, t5 # e0 :
29 or t5, a1, a1 # e0 :
31 sll a1, 32, t5 # e0 :
34 or t5, a1, a1 # .. e1 : character replication complete
57 subq t4, 1, t5 # e0 : build a mask of the bytes up to...
58 or t4, t5, t4 # e1 : ... and including the null
Dstrchr.S23 sll a1, 8, t5 # e0 : replicate the search character
25 or t5, a1, a1 # e0 :
27 sll a1, 16, t5 # e0 :
30 or t5, a1, a1 # .. e1 :
31 sll a1, 32, t5 # e0 :
33 or t5, a1, a1 # e0 :
Dev67-strchr.S33 insbl a1, 1, t5 # U : 000000000000ch00
37 or t5, t3, a1 # E : 000000000000chch
43 inswl a1, 2, t5 # E : 00000000chch0000
47 or a3, t5, t5 # E : 0000chchchch0000
52 or t5, a1, a1 # E : chchchchchchchch
Dstxcpy.S238 and a1, 7, t5 # e0 : find src misalignment
255 cmplt t4, t5, t12 # e0 :
259 mskqh t2, t5, t2 # e0 :
274 and a1, 7, t5 # .. e1 :
277 srl t12, t5, t12 # e0 : adjust final null return value
Dev6-stxcpy.S268 and a1, 7, t5 # E : find src misalignment
286 cmplt t4, t5, t12 # E :
290 mskqh t2, t5, t2 # U :
303 and a1, 7, t5 # E :
307 srl t12, t5, t12 # U : adjust final null return value
Dstxncpy.S295 and a1, 7, t5 # e0 : find src misalignment
311 1: cmplt t4, t5, t12 # e1 :
319 or t8, t10, t5 # .. e1 : test for end-of-count too
321 cmoveq a2, t5, t8 # .. e1 :
Dev6-stxncpy.S340 and a1, 7, t5 # E : find src misalignment
358 1: cmplt t4, t5, t12 # E :
366 or t8, t10, t5 # E : test for end-of-count too
369 cmoveq a2, t5, t8 # E : Latency=2, extra map slot
/arch/x86/crypto/
Dglue_helper-asm-avx2.S61 t1x, t2, t2x, t3, t3x, t4, t5) \ argument
75 add2_le128(t2, t0, t4, t3, t5); /* ab: le2 ; cd: le3 */ \
77 add2_le128(t2, t0, t4, t3, t5); \
79 add2_le128(t2, t0, t4, t3, t5); \
81 add2_le128(t2, t0, t4, t3, t5); \
83 add2_le128(t2, t0, t4, t3, t5); \
85 add2_le128(t2, t0, t4, t3, t5); \
87 add2_le128(t2, t0, t4, t3, t5); \
Dcamellia-aesni-avx2-asm_64.S66 #define roundsm32(x0, x1, x2, x3, x4, x5, x6, x7, t0, t1, t2, t3, t4, t5, t6, \ argument
73 vbroadcasti128 .Lpre_tf_lo_s1, t5; \
90 filter_8bit(x0, t5, t6, t7, t4); \
91 filter_8bit(x7, t5, t6, t7, t4); \
98 filter_8bit(x2, t5, t6, t7, t4); \
99 filter_8bit(x5, t5, t6, t7, t4); \
100 filter_8bit(x1, t5, t6, t7, t4); \
101 filter_8bit(x4, t5, t6, t7, t4); \
107 vextracti128 $1, x5, t5##_x; \
128 vaesenclast t4##_x, t5##_x, t5##_x; \
[all …]
Dcamellia-aesni-avx-asm_64.S49 #define roundsm16(x0, x1, x2, x3, x4, x5, x6, x7, t0, t1, t2, t3, t4, t5, t6, \ argument
106 vmovdqa .Lpost_tf_hi_s2, t5; \
114 filter_8bit(x1, t4, t5, t7, t2); \
115 filter_8bit(x4, t4, t5, t7, t2); \
117 vpsrldq $5, t0, t5; \
127 vpsrldq $2, t5, t7; \
163 vpsrldq $1, t5, t3; \
164 vpshufb t6, t5, t5; \
179 vpxor t5, x2, x2; \
/arch/sparc/lib/
Dmemcpy.S17 #define MOVE_BIGCHUNK(src, dst, offset, t0, t1, t2, t3, t4, t5, t6, t7) \ argument
27 st %t5, [%dst + (offset) + 0x14]; \
31 #define MOVE_BIGALIGNCHUNK(src, dst, offset, t0, t1, t2, t3, t4, t5, t6, t7) \ argument
62 #define RMOVE_BIGCHUNK(src, dst, offset, t0, t1, t2, t3, t4, t5, t6, t7) \ argument
72 st %t5, [%dst - (offset) - 0x0c]; \
76 #define RMOVE_BIGALIGNCHUNK(src, dst, offset, t0, t1, t2, t3, t4, t5, t6, t7) \ argument
100 #define SMOVE_CHUNK(src, dst, offset, t0, t1, t2, t3, t4, t5, t6, prev, shil, shir, offset2) \ argument
103 srl %t0, shir, %t5; \
106 or %t5, %prev, %t5; \
118 #define SMOVE_ALIGNCHUNK(src, dst, offset, t0, t1, t2, t3, t4, t5, t6, prev, shil, shir, offset2) \ argument
[all …]
Dchecksum_32.S18 #define CSUM_BIGCHUNK(buf, offset, sum, t0, t1, t2, t3, t4, t5) \ argument
28 addxcc t5, sum, sum; \
191 #define CSUMCOPY_BIGCHUNK_ALIGNED(src, dst, sum, off, t0, t1, t2, t3, t4, t5, t6, t7) \ argument
204 addxcc t5, sum, sum; \
213 #define CSUMCOPY_BIGCHUNK(src, dst, sum, off, t0, t1, t2, t3, t4, t5, t6, t7) \ argument
228 st t5, [dst + off + 0x14]; \
229 addxcc t5, sum, sum; \
Dblockops.S26 #define MIRROR_BLOCK(dst, src, offset, t0, t1, t2, t3, t4, t5, t6, t7) \ argument
Dcopy_user.S67 #define MOVE_BIGCHUNK(src, dst, offset, t0, t1, t2, t3, t4, t5, t6, t7) \ argument
77 st %t5, [%dst + (offset) + 0x14]; \
81 #define MOVE_BIGALIGNCHUNK(src, dst, offset, t0, t1, t2, t3, t4, t5, t6, t7) \ argument
/arch/ia64/lib/
Dcopy_page.S43 t5[PIPE_DEPTH], t6[PIPE_DEPTH], t7[PIPE_DEPTH], t8[PIPE_DEPTH]
80 (p[0]) ld8 t5[0]=[src1],16
81 (EPI) st8 [tgt1]=t5[PIPE_DEPTH-1],16
Dcopy_page_mck.S79 #define t5 t1 // alias! macro
82 #define t9 t5 // alias!
151 (p[D]) ld8 t5 = [src0], 8
158 (p[D]) st8 [dst0] = t5, 8
Dmemcpy_mck.S47 #define t5 t1 // alias! macro
51 #define t9 t5 // alias!
230 EX(.ex_handler, (p[D]) ld8 t5 = [src0], 8)
237 EX(.ex_handler, (p[D]) st8 [dst0] = t5, 8)
436 EX(.ex_handler_short, (p6) ld1 t5=[src0],2)
441 EX(.ex_handler_short, (p6) st1 [dst0]=t5,2)
480 EK(.ex_handler_short, (p10) ld1 t5=[src0],2)
488 EK(.ex_handler_short, (p10) st1 [dst0] = t5,2)
/arch/alpha/include/uapi/asm/
Dregdef.h11 #define t5 $6 macro
/arch/mips/kernel/
Dscall32-o32.S55 lw t5, TI_ADDR_LIMIT($28)
57 and t5, t4
58 bltz t5, bad_stack # -> sp is bad
68 load_a4: user_lw(t5, 16(t0)) # argument #5 from usp
74 sw t5, 16(sp) # argument #5 to ksp
161 li t5, 0
206 lw t5, 24(sp)
209 sw t5, 20(sp)
Dpm-cps.c82 t0, t1, t2, t3, t4, t5, t6, t7, enumerator
/arch/arm/mach-omap2/
Dgpmc-smc91x.c69 const int t5 = 25; /* Figure 12.2 read */ in smc91c96_gpmc_retime() local
88 dev_t.t_oe = t5 * 1000; in smc91c96_gpmc_retime()
/arch/mips/include/asm/
Dregdef.h36 #define t5 $13 macro
/arch/tile/kernel/
Dhvglue_trace.c156 #define __HV_DECL5(t5, a5, ...) t5 a5, __HV_DECL4(__VA_ARGS__) argument
165 #define __HV_PASS5(t5, a5, ...) a5, __HV_PASS4(__VA_ARGS__) argument
/arch/mips/lib/
Dcsum_partial.S33 #define t5 $13 macro
501 LOAD(t5, UNIT(5)(src), .Ll_exc_copy\@)
515 ADDC(t4, t5)
516 STORE(t5, UNIT(5)(dst), .Ls_exc\@)

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