| /drivers/macintosh/ |
| D | via-maciisi.c | 33 #define B 0 /* B-side data */ macro
139 int status = via[B] & (TIP|TREQ); in maciisi_stfu()
154 status = via[B] & (TIP|TREQ); in maciisi_stfu()
158 via[B] |= TIP; in maciisi_stfu()
165 status = via[B] & (TIP|TREQ); in maciisi_stfu()
172 if(via[B] & TREQ) in maciisi_stfu()
176 via[B] |= TACK; in maciisi_stfu()
178 via[B] &= ~TACK; in maciisi_stfu()
182 via[B] &= ~TIP; in maciisi_stfu()
200 printk(KERN_DEBUG "maciisi_init_via: initial status %x\n", via[B] & (TIP|TREQ)); in maciisi_init_via()
[all …]
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| D | via-cuda.c | 36 #define B 0 /* B-side data */ macro
265 out_8(&via[B], in_8(&via[B]) | TACK | TIP); /* negate them */ in cuda_init_via()
281 out_8(&via[B], in_8(&via[B]) & ~TACK); in cuda_init_via()
284 WAIT_FOR((in_8(&via[B]) & TREQ) == 0, "CUDA response to sync"); in cuda_init_via()
292 out_8(&via[B], in_8(&via[B]) | TACK); in cuda_init_via()
295 WAIT_FOR(in_8(&via[B]) & TREQ, "CUDA response to sync (3)"); in cuda_init_via()
299 out_8(&via[B], in_8(&via[B]) | TIP); /* should be unnecessary */ in cuda_init_via()
423 if ((in_8(&via[B]) & TREQ) == 0) in cuda_start()
429 out_8(&via[B], in_8(&via[B]) & ~TIP); in cuda_start()
476 status = (~in_8(&via[B]) & (TIP|TREQ)) | (in_8(&via[ACR]) & SR_OUT); in cuda_interrupt()
[all …]
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| D | via-macii.c | 42 #define B 0 /* B-side data */ macro
180 via[B] |= ST_IDLE; in macii_init_via()
181 last_status = via[B] & (ST_MASK|CTLR_IRQ); in macii_init_via()
364 via[B] = (via[B] & ~ST_MASK) | ST_CMD; in macii_start()
403 status = via[B] & (ST_MASK|CTLR_IRQ); in macii_interrupt()
430 via[B] = (via[B] & ~ST_MASK) | ST_EVEN; in macii_interrupt()
458 via[B] = (via[B] & ~ST_MASK) | ST_IDLE; in macii_interrupt()
463 if ( (via[B] & ST_MASK) == ST_CMD ) { in macii_interrupt()
465 via[B] = (via[B] & ~ST_MASK) | ST_EVEN; in macii_interrupt()
468 via[B] ^= ST_MASK; in macii_interrupt()
[all …]
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| D | via-pmu68k.c | 48 #define B 0 /* B-side data */ macro
194 via2[B] |= TREQ; /* negate TREQ */ in pmu_init()
513 via2[B] &= ~TREQ; /* assert TREQ */ in send_byte()
523 via2[B] &= ~TREQ; in recv_byte()
576 irq, pmu_state, (uint) via1[ACR], (uint) via2[B], data_index, data_len, adb_int_pending); in pmu_interrupt()
582 if (via2[B] & TACK) { in pmu_interrupt()
583 printk(KERN_DEBUG "PMU: SR_INT but ack still high! (%x)\n", via2[B]); in pmu_interrupt()
590 via2[B] |= TREQ; in pmu_interrupt()
592 while (!(via2[B] & TACK)) { in pmu_interrupt()
682 pmu_state, (uint) via1[ACR], (uint) via2[B], data_index, data_len, adb_int_pending); in pmu_interrupt()
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| D | via-pmu.c | 82 #define B 0 /* B-side data */ macro
530 out_8(&via[B], via[B] | TREQ); /* negate TREQ */ in init_pmu()
1171 while ((in_8(&via[B]) & TACK) == 0) { in wait_for_ack()
1189 out_8(&v[B], in_8(&v[B]) & ~TREQ); /* assert TREQ */ in send_byte()
1190 (void)in_8(&v[B]); in send_byte()
1200 out_8(&v[B], in_8(&v[B]) & ~TREQ); in recv_byte()
1201 (void)in_8(&v[B]); in recv_byte()
1453 if (via[B] & TREQ) { in pmu_sr_intr()
1454 printk(KERN_ERR "PMU: spurious SR intr (%x)\n", via[B]); in pmu_sr_intr()
1459 while ((in_8(&via[B]) & TACK) != 0) in pmu_sr_intr()
[all …]
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| /drivers/pinctrl/sunxi/ |
| D | pinctrl-sun5i-a10s.c | 136 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
140 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
144 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
149 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
154 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
159 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
164 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
169 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
174 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
179 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
[all …]
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| D | pinctrl-sun4i-a10.c | 123 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
127 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
131 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
135 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
139 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
143 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
148 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
153 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
158 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
163 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
[all …]
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| D | pinctrl-sun7i-a20.c | 146 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
150 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
154 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
158 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
163 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
167 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
172 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
177 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
182 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
187 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
[all …]
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| D | pinctrl-sun5i-a13.c | 23 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
27 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
31 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
36 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
41 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
47 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10),
53 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15),
57 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16),
61 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 17),
65 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 18),
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| D | pinctrl-sun8i-a23.c | 71 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
76 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
81 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
86 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
91 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
96 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
101 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
106 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
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| D | pinctrl-sun6i-a31.c | 218 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
225 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
230 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
235 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
240 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
246 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
253 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
260 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
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| /drivers/isdn/icn/ |
| D | Kconfig | 2 tristate "ICN 2B and 4B support"
6 company called ICN. 2B is the standard version for a single ISDN
7 line with two B-channels, 4B supports two ISDN lines. For running
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| /drivers/gpu/drm/i915/ |
| D | i915_cmd_parser.c | 111 #define B CMD_DESC_BITMASK macro
127 CMD( MI_STORE_REGISTER_MEM(1), SMI, !F, 0xFF, W | B,
134 CMD( MI_LOAD_REGISTER_MEM, SMI, !F, 0xFF, W | B,
152 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3F, B,
159 CMD( MI_CLFLUSH, SMI, !F, 0x3FF, B,
165 CMD( MI_REPORT_PERF_COUNT, SMI, !F, 0x3F, B,
171 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B,
179 CMD( MEDIA_VFE_STATE, S3D, !F, 0xFFFF, B,
188 CMD( GFX_OP_PIPE_CONTROL(5), S3D, !F, 0xFF, B,
227 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, B,
[all …]
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| /drivers/net/ethernet/sfc/ |
| D | nic.c | 190 #define REGISTER_AB(name) REGISTER(name, F, A, B)
192 #define REGISTER_BB(name) REGISTER(name, F, B, B)
193 #define REGISTER_BZ(name) REGISTER(name, F, B, Z)
327 #define REGISTER_TABLE_BB(name) REGISTER_TABLE(name, F, B, B)
328 #define REGISTER_TABLE_BZ(name) REGISTER_TABLE(name, F, B, Z)
330 REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, F, B, B, \
357 F, B, Z, 8, 1024),
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| /drivers/isdn/hardware/avm/ |
| D | Kconfig | 31 tristate "AVM T1/T1-B ISA support"
35 Note: This is a PRI card and handle 30 B-channels.
51 tristate "AVM T1/T1-B PCI support"
55 Note: This is a PRI card and handle 30 B-channels.
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| /drivers/block/paride/ |
| D | Transition-notes | 6 one in ps_set_intr() (A) and two in ps_tq_int() (B and C).
8 anything except B, since it is under if (!ps_tq_active) under
9 ps_spinlock. C is always preceded by B, since we can't reach it
10 other than through B and we don't drop ps_spinlock between them.
11 IOW, the sequence is A?(BA|BC|B)*. OTOH, number of B can not exceed
14 A and each B is preceded by either A or C. Moments when we enter
15 ps_tq_int() are sandwiched between {A,C} and B in that sequence,
16 since at any time number of B can not exceed the number of these
20 B resets ps_tq_active)*.
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| /drivers/mfd/ |
| D | tps80031.c | 99 [TPS80031_INT_WATCHDOG] = TPS80031_IRQ(B, 0),
100 [TPS80031_INT_BAT] = TPS80031_IRQ(B, 1),
101 [TPS80031_INT_SIM] = TPS80031_IRQ(B, 2),
102 [TPS80031_INT_MMC] = TPS80031_IRQ(B, 3),
103 [TPS80031_INT_RES] = TPS80031_IRQ(B, 4),
104 [TPS80031_INT_GPADC_RT] = TPS80031_IRQ(B, 5),
105 [TPS80031_INT_GPADC_SW2_EOC] = TPS80031_IRQ(B, 6),
106 [TPS80031_INT_CC_AUTOCAL] = TPS80031_IRQ(B, 7),
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| /drivers/mtd/spi-nor/ |
| D | Kconfig | 11 bool "Use small 4096 B erase sectors"
14 Many flash memories support erasing small (4096 B) sectors. Depending
22 4096 B erase size (e.g. UBIFS requires 15 KiB as a minimum).
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| /drivers/staging/media/davinci_vpfe/ |
| D | davinci-vpfe-mc.txt | 39 DAVINCI RESIZER B
109 DAVINCI CROP RESIZER--->DAVINCI RESIZER [A/B]---> SDRAM
116 DAVINCI IPIPE---> DAVINCI CROP RESIZER--->DAVINCI RESIZER [A/B]---> SDRAM
126 DAVINCI RESIZER [A/B]---> SDRAM
133 DAVINCI RESIZER [A/B]---> SDRAM
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| /drivers/s390/block/ |
| D | scm_blk_cluster.c | 60 static bool clusters_intersect(struct scm_request *A, struct scm_request *B) in clusters_intersect() argument
68 firstB = ((u64) blk_rq_pos(B->request) << 9) / CLUSTER_SIZE; in clusters_intersect()
69 lastB = (((u64) blk_rq_pos(B->request) << 9) + in clusters_intersect()
70 blk_rq_bytes(B->request) - 1) / CLUSTER_SIZE; in clusters_intersect()
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| /drivers/media/dvb-frontends/ |
| D | cxd2820r_c.c | 223 unsigned int A, B; in cxd2820r_read_snr_c() local
232 B = 650; in cxd2820r_read_snr_c()
235 B = 760; in cxd2820r_read_snr_c()
244 *snr = A * (intlog2(B / tmp) >> 5) / (CXD2820R_LOG2_E_24 >> 5) in cxd2820r_read_snr_c()
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| /drivers/net/wireless/rtl818x/ |
| D | Kconfig | 49 Wistron Neweb Corp CB-200B
52 TwinMOS Booming B Series
61 tristate "Realtek 8187 and 8187B USB support"
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| /drivers/staging/unisys/common-spar/include/channels/ |
| D | channel.h | 35 #define SIGNATURE_16(A, B) ((A) | (B<<8)) argument
36 #define SIGNATURE_32(A, B, C, D) \ argument
37 (SIGNATURE_16(A, B) | (SIGNATURE_16(C, D) << 16))
38 #define SIGNATURE_64(A, B, C, D, E, F, G, H) \ argument
39 (SIGNATURE_32(A, B, C, D) | ((u64)(SIGNATURE_32(E, F, G, H)) << 32))
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| /drivers/staging/rtl8192e/ |
| D | rtllib_crypt_wep.c | 129 u8 B = (wep->iv >> 16) & 0xff; in prism2_wep_encrypt() local
131 if (B >= 3 && B < klen) in prism2_wep_encrypt()
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| /drivers/staging/rtl8192u/ieee80211/ |
| D | ieee80211_crypt_wep.c | 130 u8 B = (wep->iv >> 16) & 0xff; in prism2_wep_encrypt() local
131 if (B >= 3 && B < klen) in prism2_wep_encrypt()
|