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Searched refs:BIT11 (Results 1 – 21 of 21) sorted by relevance

/drivers/staging/emxx_udc/
Demxx_udc.h98 #define BIT11 0x00000800 macro
188 #define EP3_INT BIT11
215 #define EP3_EN BIT11
256 #define EP0_IN_NAK_INT BIT11
269 #define EP0_STATUS_RW_BIT (BIT16|BIT15|BIT11|0xFF)
275 #define EP0_IN_NAK_EN BIT11
309 #define EPn_IPIDCLR BIT11
372 #define EPn_STOP_MODE BIT11
/drivers/staging/vt6655/
D80211hdr.h48 #define BIT11 0x00000800 macro
164 #define WLAN_GET_FC_RETRY(n) ((((unsigned short)(n) << 8) & (BIT11)) >> 11)
197 #define WLAN_GET_FC_RETRY(n) ((((unsigned short)(n)) & (BIT11)) >> 11)
Dhostap.h45 #define WLAN_RATE_54M BIT11
/drivers/staging/rtl8192e/rtl8192e/
Dr8192E_hw.h231 #define IMR_RDU BIT11
256 #define TPPoll_StopVI BIT11
386 #define RRSR_54M BIT11
/drivers/net/wireless/rtlwifi/btcoexist/
Dhalbt_precomp.h59 #define BIT11 0x00000800 macro
/drivers/staging/rtl8188eu/hal/
Dodm_RTL8188E.c92 BIT13|BIT12|BIT11, 2); in dm_trx_hw_antenna_div_init()
139 phy_set_bb_reg(adapter, 0x858, BIT13|BIT12|BIT11, 2); in dm_fast_training_init()
147 phy_set_bb_reg(adapter, 0x858, BIT13|BIT12|BIT11, 1); in dm_fast_training_init()
/drivers/staging/rtl8188eu/include/
Drtl8188e_spec.h37 #define BIT11 0x00000800 macro
562 #define RRSR_54M BIT11
631 #define IMR_HISR1_IND_INT_88E BIT11 /* HISR1 Indicator (HISR1 & HIMR1 is true, this bit is set to…
660 #define IMR_TXERR_88E BIT11 /* Tx Err Flag Int Status, write 1 clear. */
720 #define RCR_ADF BIT11 /* Accept data type frame */
Dodm_debug.h71 #define ODM_COMP_PSD BIT11
Dosdep_service.h118 #define BIT11 0x00000800 macro
Dodm.h428 ODM_BB_PSD = BIT11,
/drivers/scsi/
Dtmscsim.h181 #define BIT11 0x00000800 macro
218 #define SRB_COMPLETED BIT11
Ddc395x.h64 #define BIT11 0x00000800 macro
/drivers/staging/rtl8192u/
Dr8192U_hw.h318 #define RRSR_54M BIT11
Dr8192U.h59 #define BIT11 0x00000800 macro
107 #define COMP_QOS BIT11
/drivers/staging/rtl8192e/
Drtl819x_Qos.h35 #define BIT11 0x00000800 macro
/drivers/staging/rtl8192u/ieee80211/
Drtl819x_Qos.h15 #define BIT11 0x00000800 macro
/drivers/tty/
Dsynclink_gt.c415 #define IRQ_TXUNDER BIT11 /* HDLC */
4317 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break; in sync_mode()
4318 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break; in sync_mode()
4321 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break; in sync_mode()
4322 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break; in sync_mode()
4390 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break; in sync_mode()
4391 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break; in sync_mode()
4394 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break; in sync_mode()
4395 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break; in sync_mode()
Dsynclink.c544 #define TCSR_UNDERWAIT BIT11
562 #define MISCSTATUS_RI_LATCHED BIT11
584 #define SICR_RI_ACTIVE BIT11
586 #define SICR_RI (BIT11|BIT10)
4975 RegValue |= BIT11; in usc_set_sdlc_mode()
5173 case HDLC_PREAMBLE_LENGTH_32BITS: RegValue |= BIT11; break; in usc_set_sdlc_mode()
5174 case HDLC_PREAMBLE_LENGTH_64BITS: RegValue |= BIT11 | BIT10; break; in usc_set_sdlc_mode()
/drivers/net/wireless/rtlwifi/rtl8192de/
Dreg.h395 #define RRSR_54M BIT11
/drivers/scsi/lpfc/
Dlpfc_hw4.h685 #define LPFC_SLI4_INTR11 BIT11
/drivers/char/pcmcia/
Dsynclink_cs.c294 #define IRQ_TIMER BIT11 // timer interrupt