| /drivers/staging/emxx_udc/ |
| D | emxx_udc.h | 100 #define BIT13 0x00002000 macro
156 #define UFRAME (BIT14+BIT13+BIT12)
186 #define EP5_INT BIT13
213 #define EP5_EN BIT13
254 #define EP0_OUT_FULL BIT13
416 #define AHB_VBUS_INT BIT13 /* RW */
426 #define VBUS_INTEN BIT13 /* RW */
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| /drivers/staging/vt6655/ |
| D | 80211hdr.h | 50 #define BIT13 0x00002000 macro
166 #define WLAN_GET_FC_MOREDATA(n) ((((unsigned short)(n) << 8) & (BIT13)) >> 13)
185 #define WLAN_GET_CAP_INFO_DSSSOFDM(n) ((((n)) & BIT13) >> 13)
199 #define WLAN_GET_FC_MOREDATA(n) ((((unsigned short)(n)) & (BIT13)) >> 13)
218 #define WLAN_GET_CAP_INFO_DSSSOFDM(n) (((n) & BIT13) >> 13)
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| /drivers/staging/rtl8192e/rtl8192e/ |
| D | r8192E_hw.h | 157 #define RCR_RXFTH BIT13
229 #define IMR_BcnInt BIT13
258 #define TPPoll_StopMgt BIT13
388 #define RRSR_MCS1 BIT13
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| D | r8192E_cmdpkt.h | 30 #define ISR_BcnTimerIntr BIT13
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| /drivers/staging/rtl8188eu/hal/ |
| D | odm_RTL8188E.c | 92 BIT13|BIT12|BIT11, 2); in dm_trx_hw_antenna_div_init()
139 phy_set_bb_reg(adapter, 0x858, BIT13|BIT12|BIT11, 2); in dm_fast_training_init()
147 phy_set_bb_reg(adapter, 0x858, BIT13|BIT12|BIT11, 1); in dm_fast_training_init()
212 BIT14|BIT13|BIT12, default_ant); in rtl88eu_dm_update_rx_idle_ant()
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| D | bb_cfg.c | 701 usb_write16(adapt, REG_SYS_FUNC_EN, (u16)(regval|BIT13|BIT0|BIT1)); in rtl88eu_phy_bb_config()
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| D | usb_halinit.c | 636 phy_set_bb_reg(Adapter, rFPGA0_XAB_RFParameter, BIT13, 0x01); in _InitAntenna_Selection()
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| /drivers/net/wireless/rtlwifi/btcoexist/ |
| D | halbt_precomp.h | 61 #define BIT13 0x00002000 macro
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| /drivers/staging/rtl8192u/ |
| D | r8192U_hw.h | 154 #define RCR_RXFTH BIT13 // Rx FIFO Threshold
320 #define RRSR_MCS1 BIT13
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| D | r819xU_cmdpkt.h | 14 #define ISR_BcnTimerIntr BIT13 /* Beacon Timer Interrupt */
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| D | r8192U.h | 61 #define BIT13 0x00002000 macro
109 #define COMP_RM BIT13 /* Radio Measurement */
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| /drivers/tty/ |
| D | synclink.c | 560 #define MISCSTATUS_TXC_LATCHED BIT13
581 #define SICR_TXC_ACTIVE BIT13
583 #define SICR_TXC (BIT13|BIT12)
1176 info->cmr_value &= ~BIT13; in mgsl_isr_receive_status()
1847 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) | BIT12)); in shutdown()
4696 (unsigned short)((usc_InReg(info, IOCR) & ~(BIT13|BIT12)) | BIT12)); in usc_set_sdlc_mode()
4725 RegValue |= BIT13; in usc_set_sdlc_mode()
4760 case HDLC_ENCODING_NRZB: RegValue |= BIT13; break; in usc_set_sdlc_mode()
4762 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 | BIT13; break; in usc_set_sdlc_mode()
4764 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 | BIT13; break; in usc_set_sdlc_mode()
[all …]
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| D | synclink_gt.c | 413 #define IRQ_TXDATA BIT13
4305 val |= BIT15 + BIT13; in sync_mode()
4307 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break; in sync_mode()
4309 case MGSL_MODE_RAW: val |= BIT13; break; in sync_mode()
4380 val |= BIT15 + BIT13; in sync_mode()
4382 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break; in sync_mode()
4384 case MGSL_MODE_RAW: val |= BIT13; break; in sync_mode()
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| /drivers/staging/rtl8188eu/include/ |
| D | rtl8188e_spec.h | 39 #define BIT13 0x00002000 macro
564 #define RRSR_MCS1 BIT13
659 #define IMR_ATIMEND_E_88E BIT13 /* ATIM Window End Ext for Win7 */
718 #define RCR_AMF BIT13 /* Accept management type frame */
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| D | odm_debug.h | 73 #define ODM_COMP_RXHP BIT13
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| D | osdep_service.h | 120 #define BIT13 0x00002000 macro
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| /drivers/scsi/ |
| D | tmscsim.h | 179 #define BIT13 0x00002000 macro
220 #define DO_SYNC_NEGO BIT13
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| D | dc395x.h | 62 #define BIT13 0x00002000 macro
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| /drivers/staging/rtl8192e/ |
| D | rtl819x_Qos.h | 37 #define BIT13 0x00002000 macro
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| /drivers/staging/rtl8192u/ieee80211/ |
| D | rtl819x_Qos.h | 17 #define BIT13 0x00002000 macro
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| /drivers/net/wireless/rtlwifi/rtl8192de/ |
| D | reg.h | 397 #define RRSR_MCS1 BIT13
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| /drivers/scsi/lpfc/ |
| D | lpfc_hw4.h | 687 #define LPFC_SLI4_INTR13 BIT13
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| /drivers/char/pcmcia/ |
| D | synclink_cs.c | 292 #define IRQ_ALLSENT BIT13 // all sent
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