| /drivers/staging/rtl8192e/rtl8192e/ |
| D | rtl_cam.c | 35 ulcommand |= BIT31|BIT30; in CamResetAllEntry()
42 write_nic_dword(dev, RWCAM, BIT31|BIT16|(addr&0xff)); in write_cam()
142 TargetCommand |= BIT31|BIT16; in setKey()
180 target_command = target_command | BIT31; in CAM_read_entry()
184 if (ulStatus & BIT31) in CAM_read_entry()
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| D | r8192E_hw.h | 146 #define RCR_ONLYERLPKT BIT31
191 #define CAM_CM_SecCAMPolling BIT31
210 #define CAM_POLLINIG BIT31
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| D | rtl_dm.c | 289 (pra->upper_rssi_threshold_ratr & (~BIT31)) | ((bshort_gi_enabled) ? BIT31 : 0); in dm_check_rate_adaptive()
292 (pra->middle_rssi_threshold_ratr & (~BIT31)) | ((bshort_gi_enabled) ? BIT31 : 0); in dm_check_rate_adaptive()
296 (pra->low_rssi_threshold_ratr_40M & (~BIT31)) | ((bshort_gi_enabled) ? BIT31 : 0); in dm_check_rate_adaptive()
299 (pra->low_rssi_threshold_ratr_20M & (~BIT31)) | ((bshort_gi_enabled) ? BIT31 : 0); in dm_check_rate_adaptive()
302 (pra->ping_rssi_ratr & (~BIT31)) | ((bshort_gi_enabled) ? BIT31 : 0); in dm_check_rate_adaptive()
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| D | rtl_wx.c | 319 rt_global_debug_component &= BIT31; in r8192_wx_set_debugflag()
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| /drivers/staging/rtl8188eu/hal/ |
| D | odm_RTL8188E.c | 32 phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT31, 1); in dm_rx_hw_antena_div_init()
44 phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT31, 1); in dm_rx_hw_antena_div_init()
76 phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT31, 1); in dm_trx_hw_antenna_div_init()
132 phy_set_bb_reg(adapter, 0xb2c, BIT31, 1); in dm_fast_training_init()
154 phy_set_bb_reg(adapter, 0x878, BIT31|BIT30|BIT29, 7); in dm_fast_training_init()
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| D | odm.c | 744 phy_set_bb_reg(adapter, ODM_REG_OFDM_FA_HOLDC_11N, BIT31, 1); /* hold page C counter */ in odm_FalseAlarmCounterStatistics()
745 phy_set_bb_reg(adapter, ODM_REG_OFDM_FA_RSTD_11N, BIT31, 1); /* hold page D counter */ in odm_FalseAlarmCounterStatistics()
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| D | phy.c | 879 if (!(regeac & BIT31) && in phy_path_b_iqk()
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| /drivers/net/wireless/rtlwifi/btcoexist/ |
| D | halbt_precomp.h | 79 #define BIT31 0x80000000 macro
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| /drivers/staging/emxx_udc/ |
| D | emxx_udc.h | 118 #define BIT31 0x80000000 macro
296 #define EPn_EN BIT31
396 #define ARBITER_CTR BIT31 /* RW */
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| /drivers/staging/rtl8188eu/include/ |
| D | odm_debug.h | 83 #define ODM_COMP_INIT BIT31
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| D | osdep_service.h | 138 #define BIT31 0x80000000 macro
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| D | rtl8188e_spec.h | 57 #define BIT31 0x80000000 macro
603 #define CAM_POLLINIG BIT31
708 #define RCR_APPFCS BIT31 /* WMAC append FCS after payload */
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| D | hal_intf.h | 240 #define RF_CHANGE_BY_SW BIT31
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| /drivers/staging/rtl8192u/ |
| D | r8192U_dm.c | 348 (pra->upper_rssi_threshold_ratr & (~BIT31)) | ((bshort_gi_enabled)? BIT31:0) ; in dm_check_rate_adaptive()
351 (pra->middle_rssi_threshold_ratr & (~BIT31)) | ((bshort_gi_enabled)? BIT31:0) ; in dm_check_rate_adaptive()
356 (pra->low_rssi_threshold_ratr_40M & (~BIT31)) | ((bshort_gi_enabled)? BIT31:0) ; in dm_check_rate_adaptive()
361 (pra->low_rssi_threshold_ratr_20M & (~BIT31)) | ((bshort_gi_enabled)? BIT31:0) ; in dm_check_rate_adaptive()
365 (pra->ping_rssi_ratr & (~BIT31)) | ((bshort_gi_enabled)? BIT31:0) ; in dm_check_rate_adaptive()
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| D | r8192U_hw.h | 143 #define RCR_ONLYERLPKT BIT31 // Early Receiving based on Packet Size.
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| D | r8192U.h | 79 #define BIT31 0x80000000 macro
129 #define COMP_ERR BIT31 /* Error out, always on */
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| D | r8192U_core.c | 215 ulcommand |= BIT31|BIT30; in CamResetAllEntry()
224 write_nic_dword(dev, RWCAM, BIT31|BIT16|(addr&0xff)); in write_cam()
4886 TargetCommand |= BIT31|BIT16; in setKey()
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| /drivers/scsi/ |
| D | dc395x.h | 44 #define BIT31 0x80000000 macro
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| D | tmscsim.h | 161 #define BIT31 0x80000000 macro
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| /drivers/staging/rtl8192e/ |
| D | rtl819x_Qos.h | 55 #define BIT31 0x80000000 macro
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| D | rtllib.h | 150 #define RT_RF_LPS_LEVEL_ASPM BIT31
1884 #define RF_CHANGE_BY_SW BIT31
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| /drivers/staging/vt6655/ |
| D | 80211hdr.h | 68 #define BIT31 0x80000000 macro
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| /drivers/staging/rtl8192u/ieee80211/ |
| D | rtl819x_Qos.h | 35 #define BIT31 0x80000000 macro
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| D | ieee80211.h | 1751 #define RF_CHANGE_BY_SW BIT31
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| /drivers/scsi/lpfc/ |
| D | lpfc_hw4.h | 705 #define LPFC_SLI4_INTR31 BIT31
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