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Searched refs:BIT4 (Results 1 – 25 of 48) sorted by relevance

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/drivers/staging/rtl8188eu/include/
Dpwrseq.h80 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4|BIT3, 0}, \
89 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, \
92 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, \
105 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, \
122 PWR_CMD_WRITE, BIT3|BIT4, BIT3}, \
125 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, \
133 PWR_CMD_WRITE, BIT4, 0}, \
137 PWR_CMD_WRITE, BIT4, BIT4}, \
159 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0}, \
173 PWR_CMD_WRITE, BIT3|BIT4, BIT3}, \
[all …]
Drtl8188e_spec.h30 #define BIT4 0x00000010 macro
486 #define CmdEERPOMSEL BIT4
487 #define Cmd9346CR_9356SEL BIT4
544 #define CMD_INIT_LLT_ERR BIT4
555 #define RRSR_6M BIT4
638 #define IMR_BEDOK_88E BIT4 /* AC_BE DMA OK */
701 #define StopMgt BIT4
728 #define RCR_ADD3 BIT4 /* Accept address 3 match pkt */
1204 #define SDIO_HIMR_TXFOVW_MSK BIT4
1230 #define SDIO_HISR_TXFOVW BIT4
Dodm.h421 ODM_BB_RSSI_MONITOR = BIT4,
441 #define ODM_RTL8188E BIT4
467 ODM_RF_RX_A = BIT4,
505 ODM_AP_MODE = BIT4,
519 ODM_WM_N5G = BIT4,
Drtw_sreset.h37 #define WIFI_TX_HANG BIT4
Dodm_debug.h64 #define ODM_COMP_RSSI_MONITOR BIT4
DHal8188EPhyCfg.h95 WIRELESS_MODE_N_5G = BIT4,
Dosdep_service.h111 #define BIT4 0x00000010 macro
/drivers/net/wireless/rtlwifi/rtl8821ae/
Dpwrseq.h121 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, BIT4 \
183 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, BIT4 \
301 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
397 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
408 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0 \
426 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3), 0 \
438 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT5|BIT4), (BIT5|BIT4) \
497 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3) \
501 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3 \
504 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4 \
[all …]
/drivers/scsi/
Dtmscsim.h188 #define BIT4 0x00000010 macro
211 #define SRB_MSGIN_MULTI BIT4
228 #define PARITY_ERROR BIT4
243 #define ENABLE_TIMER BIT4
283 #define EN_TAG_QUEUEING BIT4
338 #define TAG_QUEUEING_ BIT4
345 #define NO_SEEK BIT4
393 #define COUNT_2_ZERO BIT4
402 #define SERVICE_REQUEST BIT4
425 #define PARITY_ERR_REPO BIT4
[all …]
Ddc395x.h71 #define BIT4 0x00000010 macro
132 #define PARITY_ERROR BIT4
139 #define ENABLE_TIMER BIT4
177 #define WIDE_NEGO_STATE BIT4
633 #define NO_SEEK BIT4
/drivers/staging/rtl8192e/rtl8192e/
Dr8192E_hw.h115 #define EPROM_CMD_9356SEL BIT4
219 #define SCR_SKByA2 BIT4
238 #define IMR_BKDOK BIT4
249 #define TPPoll_BQ BIT4
289 #define AcmHw_BeqStatus BIT4
379 #define RRSR_6M BIT4
Drtl_pci.c43 tmp |= BIT4; in rtl8192_parse_pci_configuration()
/drivers/staging/vt6655/
D80211hdr.h41 #define BIT4 0x00000010 macro
160 #define WLAN_GET_FC_FSTYPE(n) ((((unsigned short)(n) >> 8) & (BIT4|BIT5|BIT6|BIT7)) >> 4)
179 #define WLAN_GET_CAP_INFO_PRIVACY(n) ((((n) >> 8) & BIT4) >> 4)
193 #define WLAN_GET_FC_FSTYPE(n) ((((unsigned short)(n)) & (BIT4|BIT5|BIT6|BIT7)) >> 4)
212 #define WLAN_GET_CAP_INFO_PRIVACY(n) (((n) & BIT4) >> 4)
Dhostap.h38 #define WLAN_RATE_6M BIT4
/drivers/staging/rtl8188eu/hal/
Dodm_RTL8188E.c50 phy_set_bb_reg(adapter, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT4, 1); in dm_rx_hw_antena_div_init()
64 BIT5|BIT4|BIT3, 0); in dm_trx_hw_antenna_div_init()
82 phy_set_bb_reg(adapter, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT4, 1); in dm_trx_hw_antenna_div_init()
169 phy_set_bb_reg(adapter, 0x864, BIT5|BIT4|BIT3, 0); in dm_fast_training_init()
208 BIT5|BIT4|BIT3, default_ant); in rtl88eu_dm_update_rx_idle_ant()
217 BIT5|BIT4|BIT3, default_ant); in rtl88eu_dm_update_rx_idle_ant()
/drivers/staging/rtl8192u/
Dr8192U_hw.h187 #define SCR_SKByA2 BIT4 //Search kEY BY A2
233 #define AcmHw_BeqStatus BIT4
311 #define RRSR_6M BIT4
/drivers/video/fbdev/via/
Ddvi.c75 viafb_write_reg_mask(SR1E, VIASR, 0xF0, BIT4 + in viafb_tmds_trasmitter_identify()
340 viafb_write_reg_mask(SR2A, VIASR, 0, BIT4); in dvi_patch_skew_dvp0()
361 viafb_write_reg_mask(SR2A, VIASR, 0x10, BIT4); in dvi_patch_skew_dvp0()
Dhw.c962 viafb_write_reg_mask(CR35, VIACR, 0x10, BIT4); in load_fix_bit_crtc_reg()
1728 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5); in set_display_channel()
1732 viafb_write_reg_mask(CRD2, VIACR, 0x10, BIT4 + BIT5); in set_display_channel()
1735 viafb_write_reg_mask(CRD2, VIACR, 0x30, BIT4 + BIT5); in set_display_channel()
1740 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5); in set_display_channel()
1743 viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT4 + BIT5); in set_display_channel()
2076 BIT4); in viafb_set_dpa_gfx()
/drivers/net/wireless/rtlwifi/btcoexist/
Dhalbt_precomp.h52 #define BIT4 0x00000010 macro
Dhalbtcoutsrc.h105 #define ALGO_TRACE_FW BIT4
117 #define WIFI_P2P_GC_CONNECTED BIT4
Dhalbtc8821a2ant.h33 #define BT_INFO_8821A_2ANT_B_SCO_BUSY BIT4
Dhalbtc8723b2ant.h36 #define BT_INFO_8723B_2ANT_B_SCO_BUSY BIT4
Dhalbtc8723b1ant.h33 #define BT_INFO_8723B_1ANT_B_SCO_BUSY BIT4
Dhalbtc8192e2ant.h33 #define BT_INFO_8192E_2ANT_B_SCO_BUSY BIT4
Dhalbtc8821a1ant.h35 #define BT_INFO_8821A_1ANT_B_SCO_BUSY BIT4

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