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Searched refs:BIT6 (Results 1 – 25 of 47) sorted by relevance

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/drivers/scsi/
Dtmscsim.h186 #define BIT6 0x00000040 macro
213 #define SRB_START_ BIT6 /*;arbitration+msg_out+command_out*/
241 #define DATAIN BIT6
391 #define ILLEGAL_OP_ERR BIT6
400 #define INVALID_CMD BIT6
424 #define DIS_INT_ON_SCSI_RST BIT6
429 #define EN_FEATURE BIT6
434 #define EN_QTAG_MSG BIT6
442 #define EATER_35NS BIT6
443 #define EATER_0NS (BIT7+BIT6)
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Ddc395x.h69 #define BIT6 0x00000040 macro
137 #define DATAIN BIT6
179 #define EN_ATN_STOP BIT6
/drivers/staging/vt6655/
D80211hdr.h43 #define BIT6 0x00000040 macro
160 #define WLAN_GET_FC_FSTYPE(n) ((((unsigned short)(n) >> 8) & (BIT4|BIT5|BIT6|BIT7)) >> 4)
181 #define WLAN_GET_CAP_INFO_PBCC(n) ((((n) >> 8) & BIT6) >> 6)
193 #define WLAN_GET_FC_FSTYPE(n) ((((unsigned short)(n)) & (BIT4|BIT5|BIT6|BIT7)) >> 4)
214 #define WLAN_GET_CAP_INFO_PBCC(n) (((n) & BIT6) >> 6)
Dhostap.h40 #define WLAN_RATE_12M BIT6
/drivers/staging/rtl8188eu/include/
Drtl8188e_spec.h32 #define BIT6 0x00000040 macro
506 #define HSIMR_RON_INT_EN BIT6
513 #define HSISR_RON_INT_EN BIT6
546 #define CMD_EFUSE_PATCH_ERR BIT6
557 #define RRSR_12M BIT6
636 #define IMR_MGNTDOK_88E BIT6 /* Management Queue DMA OK */
699 #define StopBecon BIT6
725 #define RCR_CBSSID_DATA BIT6 /* Accept BSSID match (Data)*/
1206 #define SDIO_HIMR_TXBCNOK_MSK BIT6
1232 #define SDIO_HISR_TXBCNOK BIT6
Drtw_sreset.h39 #define WIFI_IF_NOT_EXIST BIT6
Dodm.h423 ODM_BB_ANT_DIV = BIT6,
469 ODM_RF_RX_C = BIT6,
507 ODM_AD_HOC = BIT6,
521 ODM_WM_AC = BIT6,
Dodm_debug.h66 #define ODM_COMP_ANT_DIV BIT6
DHal8188EPhyCfg.h96 WIRELESS_MODE_AC = BIT6
/drivers/video/fbdev/via/
Dlcd.c390 viafb_write_reg_mask(CRA2, VIACR, 0xC0, BIT7 + BIT6); in load_lcd_scaling()
625 viafb_write_reg_mask(CRD3, VIACR, 0xC0, BIT6 + BIT7); in integrated_lvds_disable()
634 viafb_write_reg_mask(CR91, VIACR, 0xC0, BIT6 + BIT7); in integrated_lvds_disable()
647 viafb_write_reg_mask(CRD2, VIACR, 0x40, BIT6); in integrated_lvds_disable()
653 viafb_write_reg_mask(CRD2, VIACR, 0xC0, BIT6 + BIT7); in integrated_lvds_disable()
677 viafb_write_reg_mask(CR91, VIACR, 0, BIT6 + BIT7); in integrated_lvds_enable()
686 viafb_write_reg_mask(CRD3, VIACR, 0, BIT6 + BIT7); in integrated_lvds_enable()
702 viafb_write_reg_mask(CRD2, VIACR, 0, BIT6); in integrated_lvds_enable()
708 viafb_write_reg_mask(CRD2, VIACR, 0, BIT6 + BIT7); in integrated_lvds_enable()
Ddvi.c69 viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT6 + BIT7); in viafb_tmds_trasmitter_identify()
76 BIT5 + BIT6 + BIT7); in viafb_tmds_trasmitter_identify()
435 viafb_write_reg_mask(CR88, VIACR, 0x00, BIT6 + BIT0); in viafb_dvi_enable()
Dhw.c1684 viafb_write_reg_mask(SR1B, VIASR, 0x00, BIT7 + BIT6); in viafb_init_dac()
1691 viafb_write_reg_mask(SR1B, VIASR, 0xC0, BIT7 + BIT6); in viafb_init_dac()
1695 viafb_write_reg_mask(CR6A, VIACR, 0x40, BIT6); in viafb_init_dac()
2048 viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6); in enable_second_display_channel()
2050 viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6); in enable_second_display_channel()
2056 viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6); in disable_second_display_channel()
2058 viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6); in disable_second_display_channel()
/drivers/staging/rtl8188eu/hal/
Drtl8188eu_led.c39 usb_write8(padapter, REG_LEDCFG2, (LedCfg&0xf0)|BIT5|BIT6); /* SW control led0 on. */ in SwLedOn()
63 usb_write8(padapter, REG_LEDCFG2, (LedCfg|BIT3|BIT5|BIT6)); in SwLedOff()
Dodm_RTL8188E.c170 phy_set_bb_reg(adapter, 0x864, BIT8|BIT7|BIT6, 1); in dm_fast_training_init()
210 BIT8|BIT7|BIT6, optional_ant); in rtl88eu_dm_update_rx_idle_ant()
214 BIT6|BIT7, default_ant); in rtl88eu_dm_update_rx_idle_ant()
219 BIT8|BIT7|BIT6, optional_ant); in rtl88eu_dm_update_rx_idle_ant()
Drtl8188e_cmd.c624 if (haldata->RegFwHwTxQCtrl&BIT6) { in rtl8188e_set_FwJoinBssReport_cmd()
630 usb_write8(adapt, REG_FWHW_TXQ_CTRL+2, (haldata->RegFwHwTxQCtrl&(~BIT6))); in rtl8188e_set_FwJoinBssReport_cmd()
631 haldata->RegFwHwTxQCtrl &= (~BIT6); in rtl8188e_set_FwJoinBssReport_cmd()
673 usb_write8(adapt, REG_FWHW_TXQ_CTRL+2, (haldata->RegFwHwTxQCtrl|BIT6)); in rtl8188e_set_FwJoinBssReport_cmd()
674 haldata->RegFwHwTxQCtrl |= BIT6; in rtl8188e_set_FwJoinBssReport_cmd()
/drivers/staging/rtl8192e/rtl8192e/
Dr8192E_hw.h236 #define IMR_MGNTDOK BIT6
251 #define TPPoll_MQ BIT6
291 #define AcmHw_VoqStatus BIT6
381 #define RRSR_12M BIT6
/drivers/net/wireless/rtlwifi/rtl8821ae/
Dpwrseq.h307 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0 \
442 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0 \
466 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 , BIT6 \
664 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0 \
/drivers/net/wireless/rtlwifi/btcoexist/
Dhalbt_precomp.h54 #define BIT6 0x00000040 macro
Dhalbtc8821a2ant.h31 #define BT_INFO_8821A_2ANT_B_A2DP BIT6
Dhalbtc8723b2ant.h34 #define BT_INFO_8723B_2ANT_B_A2DP BIT6
/drivers/staging/rtl8192u/
Dr8192U_hw.h235 #define AcmHw_VoqStatus BIT6
313 #define RRSR_12M BIT6
/drivers/char/pcmcia/
Dsynclink_cs.c299 #define IRQ_EXITHUNT BIT6 // receive frame start
300 #define IRQ_RXTIME BIT6 // rx char timeout
307 #define XFW BIT6 // transmit FIFO write enable
679 #define CMD_RXRESET BIT6 // receiver reset
927 if (status & (BIT7 + BIT6)) { in rx_ready_async()
941 else if (status & BIT6) in rx_ready_async()
1483 info->read_status_mask |= BIT7 | BIT6; in mgslpc_change_params()
1485 info->ignore_status_mask |= BIT7 | BIT6; in mgslpc_change_params()
2191 set_reg_bits(info, CHA+DAFO, BIT6); in mgslpc_break()
2193 clear_reg_bits(info, CHA+DAFO, BIT6); in mgslpc_break()
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/drivers/net/hamradio/
Dz8530.h117 #define BIT6 1 /* 6 bit/8bit sync */ macro
/drivers/tty/serial/
Dzs.h172 #define BIT6 1 /* 6 bit/8bit sync */ macro
/drivers/tty/
Dsynclinkmp.c416 #define RXINTE BIT6
422 #define IDLE BIT6
435 #define PMP BIT6
436 #define SHRT BIT6
2606 if (timerstatus0 & (BIT7 | BIT6)) in synclinkmp_interrupt()
2610 if (timerstatus1 & (BIT7 | BIT6)) in synclinkmp_interrupt()
4445 RegValue=BIT6; in async_mode()
4454 RegValue=BIT6; in async_mode()
4582 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */ in hdlc_mode()
4610 RegValue |= BIT6; in hdlc_mode()
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