| /drivers/staging/rtl8188eu/hal/ |
| D | odm_RTL8188E.c | 41 phy_set_bb_reg(adapter, ODM_REG_PIN_CTRL_11N, BIT9|BIT8, 0); in dm_rx_hw_antena_div_init()
73 phy_set_bb_reg(adapter, ODM_REG_PIN_CTRL_11N, BIT9|BIT8, 0); in dm_trx_hw_antenna_div_init()
90 BIT10|BIT9|BIT8, 1); in dm_trx_hw_antenna_div_init()
129 phy_set_bb_reg(adapter, 0x870, BIT9|BIT8, 0); in dm_fast_training_init()
138 phy_set_bb_reg(adapter, 0x858, BIT10|BIT9|BIT8, 1); in dm_fast_training_init()
146 phy_set_bb_reg(adapter, 0x858, BIT10|BIT9|BIT8, 0); in dm_fast_training_init()
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| D | odm.c | 440 pDM_Odm->bCckHighPower = (bool) phy_query_bb_reg(adapter, 0x824, BIT9); in odm_CommonInfoSelfInit()
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| /drivers/staging/vt6655/ |
| D | 80211hdr.h | 46 #define BIT9 0x00000200 macro
162 #define WLAN_GET_FC_FROMDS(n) ((((unsigned short)(n) << 8) & (BIT9)) >> 9)
195 #define WLAN_GET_FC_FROMDS(n) ((((unsigned short)(n)) & (BIT9)) >> 9)
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| D | hostap.h | 43 #define WLAN_RATE_36M BIT9
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| D | device_main.c | 2190 (Key_info & BIT8) && (Key_info & BIT9)) { //send 2/2 key in device_xmit()
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| /drivers/staging/rtl8192e/rtl8192e/ |
| D | r8192E_hw.h | 233 #define IMR_BDOK BIT9
254 #define TPPoll_StopBK BIT9
384 #define RRSR_36M BIT9
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| /drivers/net/wireless/rtlwifi/btcoexist/ |
| D | halbt_precomp.h | 57 #define BIT9 0x00000200 macro
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| D | halbtcoutsrc.h | 110 #define ALGO_TRACE_SW_EXEC BIT9
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| D | halbtc8192e2ant.c | 3266 u16tmp |= BIT9; in halbtc8192e2ant_init_hwconfig()
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| /drivers/staging/rtl8188eu/include/ |
| D | rtl8188e_spec.h | 35 #define BIT9 0x00000200 macro
560 #define RRSR_36M BIT9
633 #define IMR_CPWM2_88E BIT9 /* CPU power Mode exchange INT Status, Write 1 clear */
662 #define IMR_TXFOVW_88E BIT9 /* Transmit FIFO Overflow */
721 #define RCR_AICV BIT9 /* Accept ICV error packet */
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| D | odm_debug.h | 69 #define ODM_COMP_RATE_ADAPTIVE BIT9
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| D | osdep_service.h | 116 #define BIT9 0x00000200 macro
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| D | odm.h | 426 ODM_BB_RATE_ADAPTIVE = BIT9,
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| /drivers/scsi/ |
| D | tmscsim.h | 183 #define BIT9 0x00000200 macro
216 #define SRB_XFERPAD BIT9
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| D | dc395x.h | 66 #define BIT9 0x00000200 macro
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| /drivers/staging/rtl8192u/ |
| D | r8192U_hw.h | 316 #define RRSR_36M BIT9
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| D | r8192U.h | 57 #define BIT9 0x00000200 macro
105 #define COMP_POWER_TRACKING BIT9 /* 8190 TX Power Tracking */
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| /drivers/tty/ |
| D | synclink.c | 564 #define MISCSTATUS_DSR_LATCHED BIT9
587 #define SICR_DSR_ACTIVE BIT9
589 #define SICR_DSR (BIT9|BIT8)
1598 usc_OutDmaReg( info, CDIR, BIT9 | BIT1 ); in mgsl_isr_receive_dma()
1707 else if ( (DmaVector&(BIT10|BIT9)) == BIT10) in mgsl_interrupt()
4770 RegValue |= BIT9; in usc_set_sdlc_mode()
4772 RegValue |= ( BIT12 | BIT10 | BIT9 ); in usc_set_sdlc_mode()
4845 RegValue |= BIT9 | BIT8; in usc_set_sdlc_mode()
4847 RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8); in usc_set_sdlc_mode()
5016 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT9; break; in usc_set_sdlc_mode()
[all …]
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| D | synclink_gt.c | 417 #define IRQ_RXIDLE BIT9 /* HDLC */
418 #define IRQ_RXBREAK BIT9 /* async */
4164 val |= BIT9; in async_mode()
4204 val |= BIT9; in async_mode()
4327 case HDLC_CRC_16_CCITT: val |= BIT9; break; in sync_mode()
4328 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break; in sync_mode()
4400 case HDLC_CRC_16_CCITT: val |= BIT9; break; in sync_mode()
4401 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break; in sync_mode()
5044 if (!(*(src+1) & (BIT9 + BIT8))) { in loopback_test_rx()
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| /drivers/staging/rtl8192e/ |
| D | rtl819x_Qos.h | 33 #define BIT9 0x00000200 macro
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| /drivers/staging/rtl8192u/ieee80211/ |
| D | rtl819x_Qos.h | 13 #define BIT9 0x00000200 macro
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| /drivers/net/wireless/rtlwifi/rtl8192de/ |
| D | reg.h | 393 #define RRSR_36M BIT9
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| /drivers/scsi/lpfc/ |
| D | lpfc_hw4.h | 683 #define LPFC_SLI4_INTR9 BIT9
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| /drivers/char/pcmcia/ |
| D | synclink_cs.c | 296 #define IRQ_TXREPEAT BIT9 // tx message repeat
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