Searched refs:CMU_REG5 (Results 1 – 1 of 1) sorted by relevance
| /drivers/phy/ |
| D | phy-xgene.c | 168 #define CMU_REG5 0x0000a macro
808 cmu_clrbits(ctx, cmu_type, CMU_REG5, CMU_REG5_PLL_RESETB_MASK); in xgene_phy_sata_cfg_cmu_core()
852 cmu_rd(ctx, cmu_type, CMU_REG5, &val); in xgene_phy_sata_cfg_cmu_core()
859 cmu_wr(ctx, cmu_type, CMU_REG5, val); in xgene_phy_sata_cfg_cmu_core()
942 cmu_clrbits(ctx, cmu_type, CMU_REG5, CMU_REG5_PLL_RESETB_MASK); in xgene_phy_ssc_enable()
943 cmu_setbits(ctx, cmu_type, CMU_REG5, CMU_REG5_PLL_RESETB_MASK); in xgene_phy_ssc_enable()
1158 cmu_setbits(ctx, cmu_type, CMU_REG5, CMU_REG5_PLL_RESETB_MASK); in xgene_phy_cal_rdy_chk()
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