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Searched refs:CRD2 (Results 1 – 5 of 5) sorted by relevance

/drivers/video/fbdev/via/
Dlcd.c641 viafb_write_reg_mask(CRD2, VIACR, 0x80, BIT7); in integrated_lvds_disable()
647 viafb_write_reg_mask(CRD2, VIACR, 0x40, BIT6); in integrated_lvds_disable()
653 viafb_write_reg_mask(CRD2, VIACR, 0xC0, BIT6 + BIT7); in integrated_lvds_disable()
666 viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT0 + BIT1); in integrated_lvds_enable()
668 viafb_write_reg_mask(CRD2, VIACR, 0x03, BIT0 + BIT1); in integrated_lvds_enable()
696 viafb_write_reg_mask(CRD2, VIACR, 0, BIT7); in integrated_lvds_enable()
702 viafb_write_reg_mask(CRD2, VIACR, 0, BIT6); in integrated_lvds_enable()
708 viafb_write_reg_mask(CRD2, VIACR, 0, BIT6 + BIT7); in integrated_lvds_enable()
Ddvi.c332 viafb_write_reg(CRD2, VIACR, in viafb_dvi_disable()
333 viafb_read_reg(VIACR, CRD2) | 0x08); in viafb_dvi_disable()
470 viafb_write_reg_mask(CRD2, VIACR, 0, BIT3); in viafb_dvi_enable()
Dshare.h252 #define CRD2 0xD2 macro
Dhw.c1728 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5); in set_display_channel()
1732 viafb_write_reg_mask(CRD2, VIACR, 0x10, BIT4 + BIT5); in set_display_channel()
1735 viafb_write_reg_mask(CRD2, VIACR, 0x30, BIT4 + BIT5); in set_display_channel()
1740 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5); in set_display_channel()
1743 viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT4 + BIT5); in set_display_channel()
Dviamode.c209 {VIACR, CRD2, 0xFF, 0xFF} /* TMDS/LVDS control register. */