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Searched refs:CSR5 (Results 1 – 12 of 12) sorted by relevance

/drivers/net/ethernet/dec/tulip/
Dinterrupt.c93 if(((ioread32(tp->base_addr + CSR5)>>17)&0x07) == 4) { in tulip_refill_rx()
135 if (ioread32(tp->base_addr + CSR5) == 0xffffffff) { in tulip_poll()
140 iowrite32((RxIntr | RxNoBuf), tp->base_addr + CSR5); in tulip_poll()
276 } while ((ioread32(tp->base_addr + CSR5) & RxIntr)); in tulip_poll()
537 csr5 = ioread32(ioaddr + CSR5); in tulip_interrupt()
564 iowrite32(csr5 & 0x0001ff3f, ioaddr + CSR5); in tulip_interrupt()
568 iowrite32(csr5 & 0x0001ffff, ioaddr + CSR5); in tulip_interrupt()
580 csr5, ioread32(ioaddr + CSR5)); in tulip_interrupt()
718 iowrite32(0x0800f7ba, ioaddr + CSR5); in tulip_interrupt()
737 iowrite32(0x8001ffff, ioaddr + CSR5); in tulip_interrupt()
[all …]
Dpnic.c61 if (ioread32(ioaddr + CSR5) & TPLnkFail) { in pnic_lnk_change()
75 } else if (ioread32(ioaddr + CSR5) & TPLnkPass) { in pnic_lnk_change()
112 int csr5 = ioread32(ioaddr + CSR5); in pnic_timer()
129 ioread32(ioaddr + CSR5), in pnic_timer()
Dxircom_cb.c53 #define CSR5 0x28 macro
334 status = xr32(CSR5); in xircom_interrupt()
364 xw32(CSR5, status); in xircom_interrupt()
646 val = xr32(CSR5); /* Status register */ in link_status_changed()
653 xw32(CSR5, val); in link_status_changed()
667 if (!(xr32(CSR5) & (7 << 20))) /* transmitter disabled */ in transmit_active()
681 if (!(xr32(CSR5) & (7 << 17))) /* receiver disabled */ in receive_active()
Dtulip.h111 CSR5 = 0x28, enumerator
543 while (--i && (ioread32(ioaddr + CSR5) & (CSR5_TS|CSR5_RS))) in tulip_stop_rxtx()
548 ioread32(ioaddr + CSR5), in tulip_stop_rxtx()
Dtulip_core.c445 iowrite32(ioread32(ioaddr+CSR5)| 0x00008010, ioaddr + CSR5); in tulip_up()
453 } else if (ioread32(ioaddr + CSR5) & TPLnkPass) in tulip_up()
491 iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR5); in tulip_up()
499 ioread32(ioaddr + CSR5), in tulip_up()
557 ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR12), in tulip_tx_timeout()
566 (int)ioread32(ioaddr + CSR5), in tulip_tx_timeout()
573 ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR12)); in tulip_tx_timeout()
843 ioread32 (ioaddr + CSR5)); in tulip_close()
Dtimer.c30 ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR6), in tulip_media_task()
D21142.c207 ioread32(ioaddr + CSR5)); in t21142_lnk_change()
/drivers/net/ethernet/amd/
Dpcnet32.c208 #define CSR5 5 macro
1087 csr5 = a->read_csr(ioaddr, CSR5); in pcnet32_suspend()
1088 a->write_csr(ioaddr, CSR5, csr5 | CSR5_SUSPEND); in pcnet32_suspend()
1092 while (!(a->read_csr(ioaddr, CSR5) & CSR5_SUSPEND)) { in pcnet32_suspend()
1435 csr5 = a->read_csr(ioaddr, CSR5); in pcnet32_get_regs()
1436 a->write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND)); in pcnet32_get_regs()
2683 csr5 = lp->a->read_csr(ioaddr, CSR5); in pcnet32_set_multicast_list()
2684 lp->a->write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND)); in pcnet32_set_multicast_list()
/drivers/net/wireless/rt2x00/
Drt2400pci.h103 #define CSR5 0x0014 macro
Drt2500pci.h114 #define CSR5 0x0014 macro
Drt2400pci.c315 rt2x00mmio_register_multiwrite(rt2x00dev, CSR5, in rt2400pci_config_intf()
Drt2500pci.c321 rt2x00mmio_register_multiwrite(rt2x00dev, CSR5, in rt2500pci_config_intf()