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Searched refs:DSPFW3 (Results 1 – 9 of 9) sorted by relevance

/drivers/gpu/drm/gma500/
Dpsb_device.c191 regs->saveDSPFW3 = PSB_RVDC32(DSPFW3); in psb_save_display_registers()
229 PSB_WVDC32(regs->saveDSPFW3, DSPFW3); in psb_restore_display_registers()
Doaktrail_device.c201 regs->psb.saveDSPFW3 = PSB_RVDC32(DSPFW3); in oaktrail_save_display_registers()
315 PSB_WVDC32(regs->psb.saveDSPFW3, DSPFW3); in oaktrail_restore_display_registers()
Dcdv_device.c280 regs->cdv.saveDSPFW[2] = REG_READ(DSPFW3); in cdv_save_display_registers()
350 REG_WRITE(DSPFW3, regs->cdv.saveDSPFW[2]); in cdv_restore_display_registers()
Dcdv_intel_display.c521 REG_WRITE(DSPFW3, 0x36000000); in cdv_update_wm()
551 REG_WRITE(DSPFW3, 0x24000000); in cdv_update_wm()
Dpsb_intel_reg.h624 #define DSPFW3 0x7003c macro
Doaktrail_crtc.c339 REG_WRITE(DSPFW3, 0x0); in oaktrail_crtc_dpms()
/drivers/gpu/drm/i915/
Dintel_pm.c842 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN; in intel_set_memory_cxsr()
844 I915_WRITE(DSPFW3, val); in intel_set_memory_cxsr()
1142 reg = I915_READ(DSPFW3); in pineview_update_wm()
1145 I915_WRITE(DSPFW3, reg); in pineview_update_wm()
1151 reg = I915_READ(DSPFW3); in pineview_update_wm()
1154 I915_WRITE(DSPFW3, reg); in pineview_update_wm()
1160 reg = I915_READ(DSPFW3); in pineview_update_wm()
1163 I915_WRITE(DSPFW3, reg); in pineview_update_wm()
1444 I915_WRITE(DSPFW3, in valleyview_update_wm()
1445 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) | in valleyview_update_wm()
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Di915_debugfs.c1554 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; in i915_sr_status()
Di915_reg.h3928 #define DSPFW3 (dev_priv->info.display_mmio_offset + 0x7003c) macro