Home
last modified time | relevance | path

Searched refs:FW_BLC_SELF_EN (Results 1 – 5 of 5) sorted by relevance

/drivers/gpu/drm/gma500/
Dcdv_intel_display.c479 if (REG_READ(FW_BLC_SELF) & FW_BLC_SELF_EN) { in cdv_disable_sr()
482 REG_WRITE(FW_BLC_SELF, (REG_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN)); in cdv_disable_sr()
542 REG_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); in cdv_update_wm()
Dpsb_intel_reg.h611 #define FW_BLC_SELF_EN (1<<15) macro
/drivers/gpu/drm/i915/
Dintel_pm.c840 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0); in intel_set_memory_cxsr()
846 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) : in intel_set_memory_cxsr()
847 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN); in intel_set_memory_cxsr()
Di915_debugfs.c1550 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; in i915_sr_status()
Di915_reg.h1306 #define FW_BLC_SELF_EN (1<<15) /* 945 only */ macro