Searched refs:INTEN0 (Results 1 – 2 of 2) sorted by relevance
392 writel(VAL0|STINTEN, mmio+INTEN0); in amd8111e_set_coalesce()406 writel(VAL0|STINTEN,mmio+INTEN0); in amd8111e_set_coalesce()413 writel(STINTEN, mmio+INTEN0); in amd8111e_set_coalesce()420 writel(VAL0|STINTEN, mmio+INTEN0); in amd8111e_set_coalesce()457 SPNDINTEN | MPINTEN | SINTEN | STINTEN, mmio + INTEN0); in amd8111e_restart()459 writel(VAL3 | LCINTEN | VAL1 | TINTEN0 | VAL0 | RINTEN0, mmio + INTEN0); in amd8111e_restart()554 writel( INTEN0_CLEAR, mmio + INTEN0); in amd8111e_init_hw_default()811 writel(VAL0|RINTEN0, mmio + INTEN0); in amd8111e_rx_poll()1136 intren0 = readl(mmio + INTEN0); in amd8111e_interrupt()1152 writel(RINTEN0, mmio + INTEN0); in amd8111e_interrupt()[all …]
56 #define INTEN0 0x40 /* Interrupt0 enable register*/ macro