1 /* 2 * TI OMAP4 ISS V4L2 Driver - Register defines 3 * 4 * Copyright (C) 2012 Texas Instruments. 5 * 6 * Author: Sergio Aguirre <sergio.a.aguirre@gmail.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 */ 13 14 #ifndef _OMAP4_ISS_REGS_H_ 15 #define _OMAP4_ISS_REGS_H_ 16 17 /* ISS */ 18 #define ISS_HL_REVISION 0x0 19 20 #define ISS_HL_SYSCONFIG 0x10 21 #define ISS_HL_SYSCONFIG_IDLEMODE_SHIFT 2 22 #define ISS_HL_SYSCONFIG_IDLEMODE_FORCEIDLE 0x0 23 #define ISS_HL_SYSCONFIG_IDLEMODE_NOIDLE 0x1 24 #define ISS_HL_SYSCONFIG_IDLEMODE_SMARTIDLE 0x2 25 #define ISS_HL_SYSCONFIG_SOFTRESET (1 << 0) 26 27 #define ISS_HL_IRQSTATUS_RAW(i) (0x20 + (0x10 * (i))) 28 #define ISS_HL_IRQSTATUS(i) (0x24 + (0x10 * (i))) 29 #define ISS_HL_IRQENABLE_SET(i) (0x28 + (0x10 * (i))) 30 #define ISS_HL_IRQENABLE_CLR(i) (0x2c + (0x10 * (i))) 31 32 #define ISS_HL_IRQ_HS_VS (1 << 17) 33 #define ISS_HL_IRQ_SIMCOP(i) (1 << (12 + (i))) 34 #define ISS_HL_IRQ_BTE (1 << 11) 35 #define ISS_HL_IRQ_CBUFF (1 << 10) 36 #define ISS_HL_IRQ_CCP2(i) (1 << ((i) > 3 ? 16 : 14 + (i))) 37 #define ISS_HL_IRQ_CSIB (1 << 5) 38 #define ISS_HL_IRQ_CSIA (1 << 4) 39 #define ISS_HL_IRQ_ISP(i) (1 << (i)) 40 41 #define ISS_CTRL 0x80 42 #define ISS_CTRL_CLK_DIV_MASK (3 << 4) 43 #define ISS_CTRL_INPUT_SEL_MASK (3 << 2) 44 #define ISS_CTRL_INPUT_SEL_CSI2A (0 << 2) 45 #define ISS_CTRL_INPUT_SEL_CSI2B (1 << 2) 46 #define ISS_CTRL_SYNC_DETECT_VS_RAISING (3 << 0) 47 48 #define ISS_CLKCTRL 0x84 49 #define ISS_CLKCTRL_VPORT2_CLK (1 << 30) 50 #define ISS_CLKCTRL_VPORT1_CLK (1 << 29) 51 #define ISS_CLKCTRL_VPORT0_CLK (1 << 28) 52 #define ISS_CLKCTRL_CCP2 (1 << 4) 53 #define ISS_CLKCTRL_CSI2_B (1 << 3) 54 #define ISS_CLKCTRL_CSI2_A (1 << 2) 55 #define ISS_CLKCTRL_ISP (1 << 1) 56 #define ISS_CLKCTRL_SIMCOP (1 << 0) 57 58 #define ISS_CLKSTAT 0x88 59 #define ISS_CLKSTAT_VPORT2_CLK (1 << 30) 60 #define ISS_CLKSTAT_VPORT1_CLK (1 << 29) 61 #define ISS_CLKSTAT_VPORT0_CLK (1 << 28) 62 #define ISS_CLKSTAT_CCP2 (1 << 4) 63 #define ISS_CLKSTAT_CSI2_B (1 << 3) 64 #define ISS_CLKSTAT_CSI2_A (1 << 2) 65 #define ISS_CLKSTAT_ISP (1 << 1) 66 #define ISS_CLKSTAT_SIMCOP (1 << 0) 67 68 #define ISS_PM_STATUS 0x8c 69 #define ISS_PM_STATUS_CBUFF_PM_MASK (3 << 12) 70 #define ISS_PM_STATUS_BTE_PM_MASK (3 << 10) 71 #define ISS_PM_STATUS_SIMCOP_PM_MASK (3 << 8) 72 #define ISS_PM_STATUS_ISP_PM_MASK (3 << 6) 73 #define ISS_PM_STATUS_CCP2_PM_MASK (3 << 4) 74 #define ISS_PM_STATUS_CSI2_B_PM_MASK (3 << 2) 75 #define ISS_PM_STATUS_CSI2_A_PM_MASK (3 << 0) 76 77 #define REGISTER0 0x0 78 #define REGISTER0_HSCLOCKCONFIG (1 << 24) 79 #define REGISTER0_THS_TERM_MASK (0xff << 8) 80 #define REGISTER0_THS_TERM_SHIFT 8 81 #define REGISTER0_THS_SETTLE_MASK (0xff << 0) 82 #define REGISTER0_THS_SETTLE_SHIFT 0 83 84 #define REGISTER1 0x4 85 #define REGISTER1_RESET_DONE_CTRLCLK (1 << 29) 86 #define REGISTER1_CLOCK_MISS_DETECTOR_STATUS (1 << 25) 87 #define REGISTER1_TCLK_TERM_MASK (0x3f << 18) 88 #define REGISTER1_TCLK_TERM_SHIFT 18 89 #define REGISTER1_DPHY_HS_SYNC_PATTERN_SHIFT 10 90 #define REGISTER1_CTRLCLK_DIV_FACTOR_MASK (0x3 << 8) 91 #define REGISTER1_CTRLCLK_DIV_FACTOR_SHIFT 8 92 #define REGISTER1_TCLK_SETTLE_MASK (0xff << 0) 93 #define REGISTER1_TCLK_SETTLE_SHIFT 0 94 95 #define REGISTER2 0x8 96 97 #define CSI2_SYSCONFIG 0x10 98 #define CSI2_SYSCONFIG_MSTANDBY_MODE_MASK (3 << 12) 99 #define CSI2_SYSCONFIG_MSTANDBY_MODE_FORCE (0 << 12) 100 #define CSI2_SYSCONFIG_MSTANDBY_MODE_NO (1 << 12) 101 #define CSI2_SYSCONFIG_MSTANDBY_MODE_SMART (2 << 12) 102 #define CSI2_SYSCONFIG_SOFT_RESET (1 << 1) 103 #define CSI2_SYSCONFIG_AUTO_IDLE (1 << 0) 104 105 #define CSI2_SYSSTATUS 0x14 106 #define CSI2_SYSSTATUS_RESET_DONE (1 << 0) 107 108 #define CSI2_IRQSTATUS 0x18 109 #define CSI2_IRQENABLE 0x1c 110 111 /* Shared bits across CSI2_IRQENABLE and IRQSTATUS */ 112 113 #define CSI2_IRQ_OCP_ERR (1 << 14) 114 #define CSI2_IRQ_SHORT_PACKET (1 << 13) 115 #define CSI2_IRQ_ECC_CORRECTION (1 << 12) 116 #define CSI2_IRQ_ECC_NO_CORRECTION (1 << 11) 117 #define CSI2_IRQ_COMPLEXIO_ERR (1 << 9) 118 #define CSI2_IRQ_FIFO_OVF (1 << 8) 119 #define CSI2_IRQ_CONTEXT0 (1 << 0) 120 121 #define CSI2_CTRL 0x40 122 #define CSI2_CTRL_MFLAG_LEVH_MASK (7 << 20) 123 #define CSI2_CTRL_MFLAG_LEVH_SHIFT 20 124 #define CSI2_CTRL_MFLAG_LEVL_MASK (7 << 17) 125 #define CSI2_CTRL_MFLAG_LEVL_SHIFT 17 126 #define CSI2_CTRL_BURST_SIZE_EXPAND (1 << 16) 127 #define CSI2_CTRL_VP_CLK_EN (1 << 15) 128 #define CSI2_CTRL_NON_POSTED_WRITE (1 << 13) 129 #define CSI2_CTRL_VP_ONLY_EN (1 << 11) 130 #define CSI2_CTRL_VP_OUT_CTRL_MASK (3 << 8) 131 #define CSI2_CTRL_VP_OUT_CTRL_SHIFT 8 132 #define CSI2_CTRL_DBG_EN (1 << 7) 133 #define CSI2_CTRL_BURST_SIZE_MASK (3 << 5) 134 #define CSI2_CTRL_ENDIANNESS (1 << 4) 135 #define CSI2_CTRL_FRAME (1 << 3) 136 #define CSI2_CTRL_ECC_EN (1 << 2) 137 #define CSI2_CTRL_IF_EN (1 << 0) 138 139 #define CSI2_DBG_H 0x44 140 141 #define CSI2_COMPLEXIO_CFG 0x50 142 #define CSI2_COMPLEXIO_CFG_RESET_CTRL (1 << 30) 143 #define CSI2_COMPLEXIO_CFG_RESET_DONE (1 << 29) 144 #define CSI2_COMPLEXIO_CFG_PWD_CMD_MASK (3 << 27) 145 #define CSI2_COMPLEXIO_CFG_PWD_CMD_OFF (0 << 27) 146 #define CSI2_COMPLEXIO_CFG_PWD_CMD_ON (1 << 27) 147 #define CSI2_COMPLEXIO_CFG_PWD_CMD_ULP (2 << 27) 148 #define CSI2_COMPLEXIO_CFG_PWD_STATUS_MASK (3 << 25) 149 #define CSI2_COMPLEXIO_CFG_PWD_STATUS_OFF (0 << 25) 150 #define CSI2_COMPLEXIO_CFG_PWD_STATUS_ON (1 << 25) 151 #define CSI2_COMPLEXIO_CFG_PWD_STATUS_ULP (2 << 25) 152 #define CSI2_COMPLEXIO_CFG_PWR_AUTO (1 << 24) 153 #define CSI2_COMPLEXIO_CFG_DATA_POL(i) (1 << (((i) * 4) + 3)) 154 #define CSI2_COMPLEXIO_CFG_DATA_POSITION_MASK(i) (7 << ((i) * 4)) 155 #define CSI2_COMPLEXIO_CFG_DATA_POSITION_SHIFT(i) ((i) * 4) 156 #define CSI2_COMPLEXIO_CFG_CLOCK_POL (1 << 3) 157 #define CSI2_COMPLEXIO_CFG_CLOCK_POSITION_MASK (7 << 0) 158 #define CSI2_COMPLEXIO_CFG_CLOCK_POSITION_SHIFT 0 159 160 #define CSI2_COMPLEXIO_IRQSTATUS 0x54 161 162 #define CSI2_SHORT_PACKET 0x5c 163 164 #define CSI2_COMPLEXIO_IRQENABLE 0x60 165 166 /* Shared bits across CSI2_COMPLEXIO_IRQENABLE and IRQSTATUS */ 167 #define CSI2_COMPLEXIO_IRQ_STATEALLULPMEXIT (1 << 26) 168 #define CSI2_COMPLEXIO_IRQ_STATEALLULPMENTER (1 << 25) 169 #define CSI2_COMPLEXIO_IRQ_STATEULPM5 (1 << 24) 170 #define CSI2_COMPLEXIO_IRQ_STATEULPM4 (1 << 23) 171 #define CSI2_COMPLEXIO_IRQ_STATEULPM3 (1 << 22) 172 #define CSI2_COMPLEXIO_IRQ_STATEULPM2 (1 << 21) 173 #define CSI2_COMPLEXIO_IRQ_STATEULPM1 (1 << 20) 174 #define CSI2_COMPLEXIO_IRQ_ERRCONTROL5 (1 << 19) 175 #define CSI2_COMPLEXIO_IRQ_ERRCONTROL4 (1 << 18) 176 #define CSI2_COMPLEXIO_IRQ_ERRCONTROL3 (1 << 17) 177 #define CSI2_COMPLEXIO_IRQ_ERRCONTROL2 (1 << 16) 178 #define CSI2_COMPLEXIO_IRQ_ERRCONTROL1 (1 << 15) 179 #define CSI2_COMPLEXIO_IRQ_ERRESC5 (1 << 14) 180 #define CSI2_COMPLEXIO_IRQ_ERRESC4 (1 << 13) 181 #define CSI2_COMPLEXIO_IRQ_ERRESC3 (1 << 12) 182 #define CSI2_COMPLEXIO_IRQ_ERRESC2 (1 << 11) 183 #define CSI2_COMPLEXIO_IRQ_ERRESC1 (1 << 10) 184 #define CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS5 (1 << 9) 185 #define CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS4 (1 << 8) 186 #define CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS3 (1 << 7) 187 #define CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS2 (1 << 6) 188 #define CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS1 (1 << 5) 189 #define CSI2_COMPLEXIO_IRQ_ERRSOTHS5 (1 << 4) 190 #define CSI2_COMPLEXIO_IRQ_ERRSOTHS4 (1 << 3) 191 #define CSI2_COMPLEXIO_IRQ_ERRSOTHS3 (1 << 2) 192 #define CSI2_COMPLEXIO_IRQ_ERRSOTHS2 (1 << 1) 193 #define CSI2_COMPLEXIO_IRQ_ERRSOTHS1 (1 << 0) 194 195 #define CSI2_DBG_P 0x68 196 197 #define CSI2_TIMING 0x6c 198 #define CSI2_TIMING_FORCE_RX_MODE_IO1 (1 << 15) 199 #define CSI2_TIMING_STOP_STATE_X16_IO1 (1 << 14) 200 #define CSI2_TIMING_STOP_STATE_X4_IO1 (1 << 13) 201 #define CSI2_TIMING_STOP_STATE_COUNTER_IO1_MASK (0x1fff << 0) 202 #define CSI2_TIMING_STOP_STATE_COUNTER_IO1_SHIFT 0 203 204 #define CSI2_CTX_CTRL1(i) (0x70 + (0x20 * i)) 205 #define CSI2_CTX_CTRL1_GENERIC (1 << 30) 206 #define CSI2_CTX_CTRL1_TRANSCODE (0xf << 24) 207 #define CSI2_CTX_CTRL1_FEC_NUMBER_MASK (0xff << 16) 208 #define CSI2_CTX_CTRL1_COUNT_MASK (0xff << 8) 209 #define CSI2_CTX_CTRL1_COUNT_SHIFT 8 210 #define CSI2_CTX_CTRL1_EOF_EN (1 << 7) 211 #define CSI2_CTX_CTRL1_EOL_EN (1 << 6) 212 #define CSI2_CTX_CTRL1_CS_EN (1 << 5) 213 #define CSI2_CTX_CTRL1_COUNT_UNLOCK (1 << 4) 214 #define CSI2_CTX_CTRL1_PING_PONG (1 << 3) 215 #define CSI2_CTX_CTRL1_CTX_EN (1 << 0) 216 217 #define CSI2_CTX_CTRL2(i) (0x74 + (0x20 * i)) 218 #define CSI2_CTX_CTRL2_USER_DEF_MAP_SHIFT 13 219 #define CSI2_CTX_CTRL2_USER_DEF_MAP_MASK \ 220 (0x3 << CSI2_CTX_CTRL2_USER_DEF_MAP_SHIFT) 221 #define CSI2_CTX_CTRL2_VIRTUAL_ID_MASK (3 << 11) 222 #define CSI2_CTX_CTRL2_VIRTUAL_ID_SHIFT 11 223 #define CSI2_CTX_CTRL2_DPCM_PRED (1 << 10) 224 #define CSI2_CTX_CTRL2_FORMAT_MASK (0x3ff << 0) 225 #define CSI2_CTX_CTRL2_FORMAT_SHIFT 0 226 227 #define CSI2_CTX_DAT_OFST(i) (0x78 + (0x20 * i)) 228 #define CSI2_CTX_DAT_OFST_MASK (0xfff << 5) 229 230 #define CSI2_CTX_PING_ADDR(i) (0x7c + (0x20 * i)) 231 #define CSI2_CTX_PING_ADDR_MASK 0xffffffe0 232 233 #define CSI2_CTX_PONG_ADDR(i) (0x80 + (0x20 * i)) 234 #define CSI2_CTX_PONG_ADDR_MASK CSI2_CTX_PING_ADDR_MASK 235 236 #define CSI2_CTX_IRQENABLE(i) (0x84 + (0x20 * i)) 237 #define CSI2_CTX_IRQSTATUS(i) (0x88 + (0x20 * i)) 238 239 #define CSI2_CTX_CTRL3(i) (0x8c + (0x20 * i)) 240 #define CSI2_CTX_CTRL3_ALPHA_SHIFT 5 241 #define CSI2_CTX_CTRL3_ALPHA_MASK \ 242 (0x3fff << CSI2_CTX_CTRL3_ALPHA_SHIFT) 243 244 /* Shared bits across CSI2_CTX_IRQENABLE and IRQSTATUS */ 245 #define CSI2_CTX_IRQ_ECC_CORRECTION (1 << 8) 246 #define CSI2_CTX_IRQ_LINE_NUMBER (1 << 7) 247 #define CSI2_CTX_IRQ_FRAME_NUMBER (1 << 6) 248 #define CSI2_CTX_IRQ_CS (1 << 5) 249 #define CSI2_CTX_IRQ_LE (1 << 3) 250 #define CSI2_CTX_IRQ_LS (1 << 2) 251 #define CSI2_CTX_IRQ_FE (1 << 1) 252 #define CSI2_CTX_IRQ_FS (1 << 0) 253 254 /* ISS BTE */ 255 #define BTE_CTRL (0x0030) 256 #define BTE_CTRL_BW_LIMITER_MASK (0x3ff << 22) 257 #define BTE_CTRL_BW_LIMITER_SHIFT 22 258 259 /* ISS ISP_SYS1 */ 260 #define ISP5_REVISION (0x0000) 261 #define ISP5_SYSCONFIG (0x0010) 262 #define ISP5_SYSCONFIG_STANDBYMODE_MASK (3 << 4) 263 #define ISP5_SYSCONFIG_STANDBYMODE_FORCE (0 << 4) 264 #define ISP5_SYSCONFIG_STANDBYMODE_NO (1 << 4) 265 #define ISP5_SYSCONFIG_STANDBYMODE_SMART (2 << 4) 266 #define ISP5_SYSCONFIG_SOFTRESET (1 << 1) 267 268 #define ISP5_IRQSTATUS(i) (0x0028 + (0x10 * (i))) 269 #define ISP5_IRQENABLE_SET(i) (0x002c + (0x10 * (i))) 270 #define ISP5_IRQENABLE_CLR(i) (0x0030 + (0x10 * (i))) 271 272 /* Bits shared for ISP5_IRQ* registers */ 273 #define ISP5_IRQ_OCP_ERR (1 << 31) 274 #define ISP5_IRQ_IPIPE_INT_DPC_RNEW1 (1 << 29) 275 #define ISP5_IRQ_IPIPE_INT_DPC_RNEW0 (1 << 28) 276 #define ISP5_IRQ_IPIPE_INT_DPC_INIT (1 << 27) 277 #define ISP5_IRQ_IPIPE_INT_EOF (1 << 25) 278 #define ISP5_IRQ_H3A_INT_EOF (1 << 24) 279 #define ISP5_IRQ_RSZ_INT_EOF1 (1 << 23) 280 #define ISP5_IRQ_RSZ_INT_EOF0 (1 << 22) 281 #define ISP5_IRQ_RSZ_FIFO_IN_BLK_ERR (1 << 19) 282 #define ISP5_IRQ_RSZ_FIFO_OVF (1 << 18) 283 #define ISP5_IRQ_RSZ_INT_CYC_RSZB (1 << 17) 284 #define ISP5_IRQ_RSZ_INT_CYC_RSZA (1 << 16) 285 #define ISP5_IRQ_RSZ_INT_DMA (1 << 15) 286 #define ISP5_IRQ_RSZ_INT_LAST_PIX (1 << 14) 287 #define ISP5_IRQ_RSZ_INT_REG (1 << 13) 288 #define ISP5_IRQ_H3A_INT (1 << 12) 289 #define ISP5_IRQ_AF_INT (1 << 11) 290 #define ISP5_IRQ_AEW_INT (1 << 10) 291 #define ISP5_IRQ_IPIPEIF_IRQ (1 << 9) 292 #define ISP5_IRQ_IPIPE_INT_HST (1 << 8) 293 #define ISP5_IRQ_IPIPE_INT_BSC (1 << 7) 294 #define ISP5_IRQ_IPIPE_INT_DMA (1 << 6) 295 #define ISP5_IRQ_IPIPE_INT_LAST_PIX (1 << 5) 296 #define ISP5_IRQ_IPIPE_INT_REG (1 << 4) 297 #define ISP5_IRQ_ISIF_INT(i) (1 << (i)) 298 299 #define ISP5_CTRL (0x006c) 300 #define ISP5_CTRL_MSTANDBY (1 << 24) 301 #define ISP5_CTRL_VD_PULSE_EXT (1 << 23) 302 #define ISP5_CTRL_MSTANDBY_WAIT (1 << 20) 303 #define ISP5_CTRL_BL_CLK_ENABLE (1 << 15) 304 #define ISP5_CTRL_ISIF_CLK_ENABLE (1 << 14) 305 #define ISP5_CTRL_H3A_CLK_ENABLE (1 << 13) 306 #define ISP5_CTRL_RSZ_CLK_ENABLE (1 << 12) 307 #define ISP5_CTRL_IPIPE_CLK_ENABLE (1 << 11) 308 #define ISP5_CTRL_IPIPEIF_CLK_ENABLE (1 << 10) 309 #define ISP5_CTRL_SYNC_ENABLE (1 << 9) 310 #define ISP5_CTRL_PSYNC_CLK_SEL (1 << 8) 311 312 /* ISS ISP ISIF register offsets */ 313 #define ISIF_SYNCEN (0x0000) 314 #define ISIF_SYNCEN_DWEN (1 << 1) 315 #define ISIF_SYNCEN_SYEN (1 << 0) 316 317 #define ISIF_MODESET (0x0004) 318 #define ISIF_MODESET_INPMOD_MASK (3 << 12) 319 #define ISIF_MODESET_INPMOD_RAW (0 << 12) 320 #define ISIF_MODESET_INPMOD_YCBCR16 (1 << 12) 321 #define ISIF_MODESET_INPMOD_YCBCR8 (2 << 12) 322 #define ISIF_MODESET_CCDW_MASK (7 << 8) 323 #define ISIF_MODESET_CCDW_2BIT (2 << 8) 324 #define ISIF_MODESET_CCDMD (1 << 7) 325 #define ISIF_MODESET_SWEN (1 << 5) 326 #define ISIF_MODESET_HDPOL (1 << 3) 327 #define ISIF_MODESET_VDPOL (1 << 2) 328 329 #define ISIF_SPH (0x0018) 330 #define ISIF_SPH_MASK (0x7fff) 331 332 #define ISIF_LNH (0x001c) 333 #define ISIF_LNH_MASK (0x7fff) 334 335 #define ISIF_LNV (0x0028) 336 #define ISIF_LNV_MASK (0x7fff) 337 338 #define ISIF_HSIZE (0x0034) 339 #define ISIF_HSIZE_ADCR (1 << 12) 340 #define ISIF_HSIZE_HSIZE_MASK (0xfff) 341 342 #define ISIF_CADU (0x003c) 343 #define ISIF_CADU_MASK (0x7ff) 344 345 #define ISIF_CADL (0x0040) 346 #define ISIF_CADL_MASK (0xffff) 347 348 #define ISIF_CCOLP (0x004c) 349 #define ISIF_CCOLP_CP0_F0_R (0 << 6) 350 #define ISIF_CCOLP_CP0_F0_GR (1 << 6) 351 #define ISIF_CCOLP_CP0_F0_B (3 << 6) 352 #define ISIF_CCOLP_CP0_F0_GB (2 << 6) 353 #define ISIF_CCOLP_CP1_F0_R (0 << 4) 354 #define ISIF_CCOLP_CP1_F0_GR (1 << 4) 355 #define ISIF_CCOLP_CP1_F0_B (3 << 4) 356 #define ISIF_CCOLP_CP1_F0_GB (2 << 4) 357 #define ISIF_CCOLP_CP2_F0_R (0 << 2) 358 #define ISIF_CCOLP_CP2_F0_GR (1 << 2) 359 #define ISIF_CCOLP_CP2_F0_B (3 << 2) 360 #define ISIF_CCOLP_CP2_F0_GB (2 << 2) 361 #define ISIF_CCOLP_CP3_F0_R (0 << 0) 362 #define ISIF_CCOLP_CP3_F0_GR (1 << 0) 363 #define ISIF_CCOLP_CP3_F0_B (3 << 0) 364 #define ISIF_CCOLP_CP3_F0_GB (2 << 0) 365 366 #define ISIF_VDINT(i) (0x0070 + (i) * 4) 367 #define ISIF_VDINT_MASK (0x7fff) 368 369 #define ISIF_CGAMMAWD (0x0080) 370 #define ISIF_CGAMMAWD_GWDI_MASK (0xf << 1) 371 #define ISIF_CGAMMAWD_GWDI(bpp) ((16 - (bpp)) << 1) 372 373 #define ISIF_CCDCFG (0x0088) 374 #define ISIF_CCDCFG_Y8POS (1 << 11) 375 376 /* ISS ISP IPIPEIF register offsets */ 377 #define IPIPEIF_ENABLE (0x0000) 378 379 #define IPIPEIF_CFG1 (0x0004) 380 #define IPIPEIF_CFG1_INPSRC1_MASK (3 << 14) 381 #define IPIPEIF_CFG1_INPSRC1_VPORT_RAW (0 << 14) 382 #define IPIPEIF_CFG1_INPSRC1_SDRAM_RAW (1 << 14) 383 #define IPIPEIF_CFG1_INPSRC1_ISIF_DARKFM (2 << 14) 384 #define IPIPEIF_CFG1_INPSRC1_SDRAM_YUV (3 << 14) 385 #define IPIPEIF_CFG1_INPSRC2_MASK (3 << 2) 386 #define IPIPEIF_CFG1_INPSRC2_ISIF (0 << 2) 387 #define IPIPEIF_CFG1_INPSRC2_SDRAM_RAW (1 << 2) 388 #define IPIPEIF_CFG1_INPSRC2_ISIF_DARKFM (2 << 2) 389 #define IPIPEIF_CFG1_INPSRC2_SDRAM_YUV (3 << 2) 390 391 #define IPIPEIF_CFG2 (0x0030) 392 #define IPIPEIF_CFG2_YUV8P (1 << 7) 393 #define IPIPEIF_CFG2_YUV8 (1 << 6) 394 #define IPIPEIF_CFG2_YUV16 (1 << 3) 395 #define IPIPEIF_CFG2_VDPOL (1 << 2) 396 #define IPIPEIF_CFG2_HDPOL (1 << 1) 397 #define IPIPEIF_CFG2_INTSW (1 << 0) 398 399 #define IPIPEIF_CLKDIV (0x0040) 400 401 /* ISS ISP IPIPE register offsets */ 402 #define IPIPE_SRC_EN (0x0000) 403 #define IPIPE_SRC_EN_EN (1 << 0) 404 405 #define IPIPE_SRC_MODE (0x0004) 406 #define IPIPE_SRC_MODE_WRT (1 << 1) 407 #define IPIPE_SRC_MODE_OST (1 << 0) 408 409 #define IPIPE_SRC_FMT (0x0008) 410 #define IPIPE_SRC_FMT_RAW2YUV (0 << 0) 411 #define IPIPE_SRC_FMT_RAW2RAW (1 << 0) 412 #define IPIPE_SRC_FMT_RAW2STATS (2 << 0) 413 #define IPIPE_SRC_FMT_YUV2YUV (3 << 0) 414 415 #define IPIPE_SRC_COL (0x000c) 416 #define IPIPE_SRC_COL_OO_R (0 << 6) 417 #define IPIPE_SRC_COL_OO_GR (1 << 6) 418 #define IPIPE_SRC_COL_OO_B (3 << 6) 419 #define IPIPE_SRC_COL_OO_GB (2 << 6) 420 #define IPIPE_SRC_COL_OE_R (0 << 4) 421 #define IPIPE_SRC_COL_OE_GR (1 << 4) 422 #define IPIPE_SRC_COL_OE_B (3 << 4) 423 #define IPIPE_SRC_COL_OE_GB (2 << 4) 424 #define IPIPE_SRC_COL_EO_R (0 << 2) 425 #define IPIPE_SRC_COL_EO_GR (1 << 2) 426 #define IPIPE_SRC_COL_EO_B (3 << 2) 427 #define IPIPE_SRC_COL_EO_GB (2 << 2) 428 #define IPIPE_SRC_COL_EE_R (0 << 0) 429 #define IPIPE_SRC_COL_EE_GR (1 << 0) 430 #define IPIPE_SRC_COL_EE_B (3 << 0) 431 #define IPIPE_SRC_COL_EE_GB (2 << 0) 432 433 #define IPIPE_SRC_VPS (0x0010) 434 #define IPIPE_SRC_VPS_MASK (0xffff) 435 436 #define IPIPE_SRC_VSZ (0x0014) 437 #define IPIPE_SRC_VSZ_MASK (0x1fff) 438 439 #define IPIPE_SRC_HPS (0x0018) 440 #define IPIPE_SRC_HPS_MASK (0xffff) 441 442 #define IPIPE_SRC_HSZ (0x001c) 443 #define IPIPE_SRC_HSZ_MASK (0x1ffe) 444 445 #define IPIPE_SEL_SBU (0x0020) 446 447 #define IPIPE_SRC_STA (0x0024) 448 449 #define IPIPE_GCK_MMR (0x0028) 450 #define IPIPE_GCK_MMR_REG (1 << 0) 451 452 #define IPIPE_GCK_PIX (0x002c) 453 #define IPIPE_GCK_PIX_G3 (1 << 3) 454 #define IPIPE_GCK_PIX_G2 (1 << 2) 455 #define IPIPE_GCK_PIX_G1 (1 << 1) 456 #define IPIPE_GCK_PIX_G0 (1 << 0) 457 458 #define IPIPE_DPC_LUT_EN (0x0034) 459 #define IPIPE_DPC_LUT_SEL (0x0038) 460 #define IPIPE_DPC_LUT_ADR (0x003c) 461 #define IPIPE_DPC_LUT_SIZ (0x0040) 462 463 #define IPIPE_DPC_OTF_EN (0x0044) 464 #define IPIPE_DPC_OTF_TYP (0x0048) 465 #define IPIPE_DPC_OTF_2_D_THR_R (0x004c) 466 #define IPIPE_DPC_OTF_2_D_THR_GR (0x0050) 467 #define IPIPE_DPC_OTF_2_D_THR_GB (0x0054) 468 #define IPIPE_DPC_OTF_2_D_THR_B (0x0058) 469 #define IPIPE_DPC_OTF_2_C_THR_R (0x005c) 470 #define IPIPE_DPC_OTF_2_C_THR_GR (0x0060) 471 #define IPIPE_DPC_OTF_2_C_THR_GB (0x0064) 472 #define IPIPE_DPC_OTF_2_C_THR_B (0x0068) 473 #define IPIPE_DPC_OTF_3_SHF (0x006c) 474 #define IPIPE_DPC_OTF_3_D_THR (0x0070) 475 #define IPIPE_DPC_OTF_3_D_SPL (0x0074) 476 #define IPIPE_DPC_OTF_3_D_MIN (0x0078) 477 #define IPIPE_DPC_OTF_3_D_MAX (0x007c) 478 #define IPIPE_DPC_OTF_3_C_THR (0x0080) 479 #define IPIPE_DPC_OTF_3_C_SLP (0x0084) 480 #define IPIPE_DPC_OTF_3_C_MIN (0x0088) 481 #define IPIPE_DPC_OTF_3_C_MAX (0x008c) 482 483 #define IPIPE_LSC_VOFT (0x0090) 484 #define IPIPE_LSC_VA2 (0x0094) 485 #define IPIPE_LSC_VA1 (0x0098) 486 #define IPIPE_LSC_VS (0x009c) 487 #define IPIPE_LSC_HOFT (0x00a0) 488 #define IPIPE_LSC_HA2 (0x00a4) 489 #define IPIPE_LSC_HA1 (0x00a8) 490 #define IPIPE_LSC_HS (0x00ac) 491 #define IPIPE_LSC_GAN_R (0x00b0) 492 #define IPIPE_LSC_GAN_GR (0x00b4) 493 #define IPIPE_LSC_GAN_GB (0x00b8) 494 #define IPIPE_LSC_GAN_B (0x00bc) 495 #define IPIPE_LSC_OFT_R (0x00c0) 496 #define IPIPE_LSC_OFT_GR (0x00c4) 497 #define IPIPE_LSC_OFT_GB (0x00c8) 498 #define IPIPE_LSC_OFT_B (0x00cc) 499 #define IPIPE_LSC_SHF (0x00d0) 500 #define IPIPE_LSC_MAX (0x00d4) 501 502 #define IPIPE_D2F_1ST_EN (0x00d8) 503 #define IPIPE_D2F_1ST_TYP (0x00dc) 504 #define IPIPE_D2F_1ST_THR_00 (0x00e0) 505 #define IPIPE_D2F_1ST_THR_01 (0x00e4) 506 #define IPIPE_D2F_1ST_THR_02 (0x00e8) 507 #define IPIPE_D2F_1ST_THR_03 (0x00ec) 508 #define IPIPE_D2F_1ST_THR_04 (0x00f0) 509 #define IPIPE_D2F_1ST_THR_05 (0x00f4) 510 #define IPIPE_D2F_1ST_THR_06 (0x00f8) 511 #define IPIPE_D2F_1ST_THR_07 (0x00fc) 512 #define IPIPE_D2F_1ST_STR_00 (0x0100) 513 #define IPIPE_D2F_1ST_STR_01 (0x0104) 514 #define IPIPE_D2F_1ST_STR_02 (0x0108) 515 #define IPIPE_D2F_1ST_STR_03 (0x010c) 516 #define IPIPE_D2F_1ST_STR_04 (0x0110) 517 #define IPIPE_D2F_1ST_STR_05 (0x0114) 518 #define IPIPE_D2F_1ST_STR_06 (0x0118) 519 #define IPIPE_D2F_1ST_STR_07 (0x011c) 520 #define IPIPE_D2F_1ST_SPR_00 (0x0120) 521 #define IPIPE_D2F_1ST_SPR_01 (0x0124) 522 #define IPIPE_D2F_1ST_SPR_02 (0x0128) 523 #define IPIPE_D2F_1ST_SPR_03 (0x012c) 524 #define IPIPE_D2F_1ST_SPR_04 (0x0130) 525 #define IPIPE_D2F_1ST_SPR_05 (0x0134) 526 #define IPIPE_D2F_1ST_SPR_06 (0x0138) 527 #define IPIPE_D2F_1ST_SPR_07 (0x013c) 528 #define IPIPE_D2F_1ST_EDG_MIN (0x0140) 529 #define IPIPE_D2F_1ST_EDG_MAX (0x0144) 530 #define IPIPE_D2F_2ND_EN (0x0148) 531 #define IPIPE_D2F_2ND_TYP (0x014c) 532 #define IPIPE_D2F_2ND_THR00 (0x0150) 533 #define IPIPE_D2F_2ND_THR01 (0x0154) 534 #define IPIPE_D2F_2ND_THR02 (0x0158) 535 #define IPIPE_D2F_2ND_THR03 (0x015c) 536 #define IPIPE_D2F_2ND_THR04 (0x0160) 537 #define IPIPE_D2F_2ND_THR05 (0x0164) 538 #define IPIPE_D2F_2ND_THR06 (0x0168) 539 #define IPIPE_D2F_2ND_THR07 (0x016c) 540 #define IPIPE_D2F_2ND_STR_00 (0x0170) 541 #define IPIPE_D2F_2ND_STR_01 (0x0174) 542 #define IPIPE_D2F_2ND_STR_02 (0x0178) 543 #define IPIPE_D2F_2ND_STR_03 (0x017c) 544 #define IPIPE_D2F_2ND_STR_04 (0x0180) 545 #define IPIPE_D2F_2ND_STR_05 (0x0184) 546 #define IPIPE_D2F_2ND_STR_06 (0x0188) 547 #define IPIPE_D2F_2ND_STR_07 (0x018c) 548 #define IPIPE_D2F_2ND_SPR_00 (0x0190) 549 #define IPIPE_D2F_2ND_SPR_01 (0x0194) 550 #define IPIPE_D2F_2ND_SPR_02 (0x0198) 551 #define IPIPE_D2F_2ND_SPR_03 (0x019c) 552 #define IPIPE_D2F_2ND_SPR_04 (0x01a0) 553 #define IPIPE_D2F_2ND_SPR_05 (0x01a4) 554 #define IPIPE_D2F_2ND_SPR_06 (0x01a8) 555 #define IPIPE_D2F_2ND_SPR_07 (0x01ac) 556 #define IPIPE_D2F_2ND_EDG_MIN (0x01b0) 557 #define IPIPE_D2F_2ND_EDG_MAX (0x01b4) 558 559 #define IPIPE_GIC_EN (0x01b8) 560 #define IPIPE_GIC_TYP (0x01bc) 561 #define IPIPE_GIC_GAN (0x01c0) 562 #define IPIPE_GIC_NFGAIN (0x01c4) 563 #define IPIPE_GIC_THR (0x01c8) 564 #define IPIPE_GIC_SLP (0x01cc) 565 566 #define IPIPE_WB2_OFT_R (0x01d0) 567 #define IPIPE_WB2_OFT_GR (0x01d4) 568 #define IPIPE_WB2_OFT_GB (0x01d8) 569 #define IPIPE_WB2_OFT_B (0x01dc) 570 571 #define IPIPE_WB2_WGN_R (0x01e0) 572 #define IPIPE_WB2_WGN_GR (0x01e4) 573 #define IPIPE_WB2_WGN_GB (0x01e8) 574 #define IPIPE_WB2_WGN_B (0x01ec) 575 576 #define IPIPE_CFA_MODE (0x01f0) 577 #define IPIPE_CFA_2DIR_HPF_THR (0x01f4) 578 #define IPIPE_CFA_2DIR_HPF_SLP (0x01f8) 579 #define IPIPE_CFA_2DIR_MIX_THR (0x01fc) 580 #define IPIPE_CFA_2DIR_MIX_SLP (0x0200) 581 #define IPIPE_CFA_2DIR_DIR_TRH (0x0204) 582 #define IPIPE_CFA_2DIR_DIR_SLP (0x0208) 583 #define IPIPE_CFA_2DIR_NDWT (0x020c) 584 #define IPIPE_CFA_MONO_HUE_FRA (0x0210) 585 #define IPIPE_CFA_MONO_EDG_THR (0x0214) 586 #define IPIPE_CFA_MONO_THR_MIN (0x0218) 587 588 #define IPIPE_CFA_MONO_THR_SLP (0x021c) 589 #define IPIPE_CFA_MONO_SLP_MIN (0x0220) 590 #define IPIPE_CFA_MONO_SLP_SLP (0x0224) 591 #define IPIPE_CFA_MONO_LPWT (0x0228) 592 593 #define IPIPE_RGB1_MUL_RR (0x022c) 594 #define IPIPE_RGB1_MUL_GR (0x0230) 595 #define IPIPE_RGB1_MUL_BR (0x0234) 596 #define IPIPE_RGB1_MUL_RG (0x0238) 597 #define IPIPE_RGB1_MUL_GG (0x023c) 598 #define IPIPE_RGB1_MUL_BG (0x0240) 599 #define IPIPE_RGB1_MUL_RB (0x0244) 600 #define IPIPE_RGB1_MUL_GB (0x0248) 601 #define IPIPE_RGB1_MUL_BB (0x024c) 602 #define IPIPE_RGB1_OFT_OR (0x0250) 603 #define IPIPE_RGB1_OFT_OG (0x0254) 604 #define IPIPE_RGB1_OFT_OB (0x0258) 605 #define IPIPE_GMM_CFG (0x025c) 606 #define IPIPE_RGB2_MUL_RR (0x0260) 607 #define IPIPE_RGB2_MUL_GR (0x0264) 608 #define IPIPE_RGB2_MUL_BR (0x0268) 609 #define IPIPE_RGB2_MUL_RG (0x026c) 610 #define IPIPE_RGB2_MUL_GG (0x0270) 611 #define IPIPE_RGB2_MUL_BG (0x0274) 612 #define IPIPE_RGB2_MUL_RB (0x0278) 613 #define IPIPE_RGB2_MUL_GB (0x027c) 614 #define IPIPE_RGB2_MUL_BB (0x0280) 615 #define IPIPE_RGB2_OFT_OR (0x0284) 616 #define IPIPE_RGB2_OFT_OG (0x0288) 617 #define IPIPE_RGB2_OFT_OB (0x028c) 618 619 #define IPIPE_YUV_ADJ (0x0294) 620 #define IPIPE_YUV_MUL_RY (0x0298) 621 #define IPIPE_YUV_MUL_GY (0x029c) 622 #define IPIPE_YUV_MUL_BY (0x02a0) 623 #define IPIPE_YUV_MUL_RCB (0x02a4) 624 #define IPIPE_YUV_MUL_GCB (0x02a8) 625 #define IPIPE_YUV_MUL_BCB (0x02ac) 626 #define IPIPE_YUV_MUL_RCR (0x02b0) 627 #define IPIPE_YUV_MUL_GCR (0x02b4) 628 #define IPIPE_YUV_MUL_BCR (0x02b8) 629 #define IPIPE_YUV_OFT_Y (0x02bc) 630 #define IPIPE_YUV_OFT_CB (0x02c0) 631 #define IPIPE_YUV_OFT_CR (0x02c4) 632 633 #define IPIPE_YUV_PHS (0x02c8) 634 #define IPIPE_YUV_PHS_LPF (1 << 1) 635 #define IPIPE_YUV_PHS_POS (1 << 0) 636 637 #define IPIPE_YEE_EN (0x02d4) 638 #define IPIPE_YEE_TYP (0x02d8) 639 #define IPIPE_YEE_SHF (0x02dc) 640 #define IPIPE_YEE_MUL_00 (0x02e0) 641 #define IPIPE_YEE_MUL_01 (0x02e4) 642 #define IPIPE_YEE_MUL_02 (0x02e8) 643 #define IPIPE_YEE_MUL_10 (0x02ec) 644 #define IPIPE_YEE_MUL_11 (0x02f0) 645 #define IPIPE_YEE_MUL_12 (0x02f4) 646 #define IPIPE_YEE_MUL_20 (0x02f8) 647 #define IPIPE_YEE_MUL_21 (0x02fc) 648 #define IPIPE_YEE_MUL_22 (0x0300) 649 #define IPIPE_YEE_THR (0x0304) 650 #define IPIPE_YEE_E_GAN (0x0308) 651 #define IPIPE_YEE_E_THR_1 (0x030c) 652 #define IPIPE_YEE_E_THR_2 (0x0310) 653 #define IPIPE_YEE_G_GAN (0x0314) 654 #define IPIPE_YEE_G_OFT (0x0318) 655 656 #define IPIPE_CAR_EN (0x031c) 657 #define IPIPE_CAR_TYP (0x0320) 658 #define IPIPE_CAR_SW (0x0324) 659 #define IPIPE_CAR_HPF_TYP (0x0328) 660 #define IPIPE_CAR_HPF_SHF (0x032c) 661 #define IPIPE_CAR_HPF_THR (0x0330) 662 #define IPIPE_CAR_GN1_GAN (0x0334) 663 #define IPIPE_CAR_GN1_SHF (0x0338) 664 #define IPIPE_CAR_GN1_MIN (0x033c) 665 #define IPIPE_CAR_GN2_GAN (0x0340) 666 #define IPIPE_CAR_GN2_SHF (0x0344) 667 #define IPIPE_CAR_GN2_MIN (0x0348) 668 #define IPIPE_CGS_EN (0x034c) 669 #define IPIPE_CGS_GN1_L_THR (0x0350) 670 #define IPIPE_CGS_GN1_L_GAIN (0x0354) 671 #define IPIPE_CGS_GN1_L_SHF (0x0358) 672 #define IPIPE_CGS_GN1_L_MIN (0x035c) 673 #define IPIPE_CGS_GN1_H_THR (0x0360) 674 #define IPIPE_CGS_GN1_H_GAIN (0x0364) 675 #define IPIPE_CGS_GN1_H_SHF (0x0368) 676 #define IPIPE_CGS_GN1_H_MIN (0x036c) 677 #define IPIPE_CGS_GN2_L_THR (0x0370) 678 #define IPIPE_CGS_GN2_L_GAIN (0x0374) 679 #define IPIPE_CGS_GN2_L_SHF (0x0378) 680 #define IPIPE_CGS_GN2_L_MIN (0x037c) 681 682 #define IPIPE_BOX_EN (0x0380) 683 #define IPIPE_BOX_MODE (0x0384) 684 #define IPIPE_BOX_TYP (0x0388) 685 #define IPIPE_BOX_SHF (0x038c) 686 #define IPIPE_BOX_SDR_SAD_H (0x0390) 687 #define IPIPE_BOX_SDR_SAD_L (0x0394) 688 689 #define IPIPE_HST_EN (0x039c) 690 #define IPIPE_HST_MODE (0x03a0) 691 #define IPIPE_HST_SEL (0x03a4) 692 #define IPIPE_HST_PARA (0x03a8) 693 #define IPIPE_HST_0_VPS (0x03ac) 694 #define IPIPE_HST_0_VSZ (0x03b0) 695 #define IPIPE_HST_0_HPS (0x03b4) 696 #define IPIPE_HST_0_HSZ (0x03b8) 697 #define IPIPE_HST_1_VPS (0x03bc) 698 #define IPIPE_HST_1_VSZ (0x03c0) 699 #define IPIPE_HST_1_HPS (0x03c4) 700 #define IPIPE_HST_1_HSZ (0x03c8) 701 #define IPIPE_HST_2_VPS (0x03cc) 702 #define IPIPE_HST_2_VSZ (0x03d0) 703 #define IPIPE_HST_2_HPS (0x03d4) 704 #define IPIPE_HST_2_HSZ (0x03d8) 705 #define IPIPE_HST_3_VPS (0x03dc) 706 #define IPIPE_HST_3_VSZ (0x03e0) 707 #define IPIPE_HST_3_HPS (0x03e4) 708 #define IPIPE_HST_3_HSZ (0x03e8) 709 #define IPIPE_HST_TBL (0x03ec) 710 #define IPIPE_HST_MUL_R (0x03f0) 711 #define IPIPE_HST_MUL_GR (0x03f4) 712 #define IPIPE_HST_MUL_GB (0x03f8) 713 #define IPIPE_HST_MUL_B (0x03fc) 714 715 #define IPIPE_BSC_EN (0x0400) 716 #define IPIPE_BSC_MODE (0x0404) 717 #define IPIPE_BSC_TYP (0x0408) 718 #define IPIPE_BSC_ROW_VCT (0x040c) 719 #define IPIPE_BSC_ROW_SHF (0x0410) 720 #define IPIPE_BSC_ROW_VPO (0x0414) 721 #define IPIPE_BSC_ROW_VNU (0x0418) 722 #define IPIPE_BSC_ROW_VSKIP (0x041c) 723 #define IPIPE_BSC_ROW_HPO (0x0420) 724 #define IPIPE_BSC_ROW_HNU (0x0424) 725 #define IPIPE_BSC_ROW_HSKIP (0x0428) 726 #define IPIPE_BSC_COL_VCT (0x042c) 727 #define IPIPE_BSC_COL_SHF (0x0430) 728 #define IPIPE_BSC_COL_VPO (0x0434) 729 #define IPIPE_BSC_COL_VNU (0x0438) 730 #define IPIPE_BSC_COL_VSKIP (0x043c) 731 #define IPIPE_BSC_COL_HPO (0x0440) 732 #define IPIPE_BSC_COL_HNU (0x0444) 733 #define IPIPE_BSC_COL_HSKIP (0x0448) 734 735 #define IPIPE_BSC_EN (0x0400) 736 737 /* ISS ISP Resizer register offsets */ 738 #define RSZ_REVISION (0x0000) 739 #define RSZ_SYSCONFIG (0x0004) 740 #define RSZ_SYSCONFIG_RSZB_CLK_EN (1 << 9) 741 #define RSZ_SYSCONFIG_RSZA_CLK_EN (1 << 8) 742 743 #define RSZ_IN_FIFO_CTRL (0x000c) 744 #define RSZ_IN_FIFO_CTRL_THRLD_LOW_MASK (0x1ff << 16) 745 #define RSZ_IN_FIFO_CTRL_THRLD_LOW_SHIFT 16 746 #define RSZ_IN_FIFO_CTRL_THRLD_HIGH_MASK (0x1ff << 0) 747 #define RSZ_IN_FIFO_CTRL_THRLD_HIGH_SHIFT 0 748 749 #define RSZ_FRACDIV (0x0008) 750 #define RSZ_FRACDIV_MASK (0xffff) 751 752 #define RSZ_SRC_EN (0x0020) 753 #define RSZ_SRC_EN_SRC_EN (1 << 0) 754 755 #define RSZ_SRC_MODE (0x0024) 756 #define RSZ_SRC_MODE_OST (1 << 0) 757 #define RSZ_SRC_MODE_WRT (1 << 1) 758 759 #define RSZ_SRC_FMT0 (0x0028) 760 #define RSZ_SRC_FMT0_BYPASS (1 << 1) 761 #define RSZ_SRC_FMT0_SEL (1 << 0) 762 763 #define RSZ_SRC_FMT1 (0x002c) 764 #define RSZ_SRC_FMT1_IN420 (1 << 1) 765 766 #define RSZ_SRC_VPS (0x0030) 767 #define RSZ_SRC_VSZ (0x0034) 768 #define RSZ_SRC_HPS (0x0038) 769 #define RSZ_SRC_HSZ (0x003c) 770 #define RSZ_DMA_RZA (0x0040) 771 #define RSZ_DMA_RZB (0x0044) 772 #define RSZ_DMA_STA (0x0048) 773 #define RSZ_GCK_MMR (0x004c) 774 #define RSZ_GCK_MMR_MMR (1 << 0) 775 776 #define RSZ_GCK_SDR (0x0054) 777 #define RSZ_GCK_SDR_CORE (1 << 0) 778 779 #define RSZ_IRQ_RZA (0x0058) 780 #define RSZ_IRQ_RZA_MASK (0x1fff) 781 782 #define RSZ_IRQ_RZB (0x005c) 783 #define RSZ_IRQ_RZB_MASK (0x1fff) 784 785 #define RSZ_YUV_Y_MIN (0x0060) 786 #define RSZ_YUV_Y_MAX (0x0064) 787 #define RSZ_YUV_C_MIN (0x0068) 788 #define RSZ_YUV_C_MAX (0x006c) 789 790 #define RSZ_SEQ (0x0074) 791 #define RSZ_SEQ_HRVB (1 << 2) 792 #define RSZ_SEQ_HRVA (1 << 0) 793 794 #define RZA_EN (0x0078) 795 #define RZA_MODE (0x007c) 796 #define RZA_MODE_ONE_SHOT (1 << 0) 797 798 #define RZA_420 (0x0080) 799 #define RZA_I_VPS (0x0084) 800 #define RZA_I_HPS (0x0088) 801 #define RZA_O_VSZ (0x008c) 802 #define RZA_O_HSZ (0x0090) 803 #define RZA_V_PHS_Y (0x0094) 804 #define RZA_V_PHS_C (0x0098) 805 #define RZA_V_DIF (0x009c) 806 #define RZA_V_TYP (0x00a0) 807 #define RZA_V_LPF (0x00a4) 808 #define RZA_H_PHS (0x00a8) 809 #define RZA_H_DIF (0x00b0) 810 #define RZA_H_TYP (0x00b4) 811 #define RZA_H_LPF (0x00b8) 812 #define RZA_DWN_EN (0x00bc) 813 #define RZA_SDR_Y_BAD_H (0x00d0) 814 #define RZA_SDR_Y_BAD_L (0x00d4) 815 #define RZA_SDR_Y_SAD_H (0x00d8) 816 #define RZA_SDR_Y_SAD_L (0x00dc) 817 #define RZA_SDR_Y_OFT (0x00e0) 818 #define RZA_SDR_Y_PTR_S (0x00e4) 819 #define RZA_SDR_Y_PTR_E (0x00e8) 820 #define RZA_SDR_C_BAD_H (0x00ec) 821 #define RZA_SDR_C_BAD_L (0x00f0) 822 #define RZA_SDR_C_SAD_H (0x00f4) 823 #define RZA_SDR_C_SAD_L (0x00f8) 824 #define RZA_SDR_C_OFT (0x00fc) 825 #define RZA_SDR_C_PTR_S (0x0100) 826 #define RZA_SDR_C_PTR_E (0x0104) 827 828 #define RZB_EN (0x0108) 829 #define RZB_MODE (0x010c) 830 #define RZB_420 (0x0110) 831 #define RZB_I_VPS (0x0114) 832 #define RZB_I_HPS (0x0118) 833 #define RZB_O_VSZ (0x011c) 834 #define RZB_O_HSZ (0x0120) 835 836 #define RZB_V_DIF (0x012c) 837 #define RZB_V_TYP (0x0130) 838 #define RZB_V_LPF (0x0134) 839 840 #define RZB_H_DIF (0x0140) 841 #define RZB_H_TYP (0x0144) 842 #define RZB_H_LPF (0x0148) 843 844 #define RZB_SDR_Y_BAD_H (0x0160) 845 #define RZB_SDR_Y_BAD_L (0x0164) 846 #define RZB_SDR_Y_SAD_H (0x0168) 847 #define RZB_SDR_Y_SAD_L (0x016c) 848 #define RZB_SDR_Y_OFT (0x0170) 849 #define RZB_SDR_Y_PTR_S (0x0174) 850 #define RZB_SDR_Y_PTR_E (0x0178) 851 #define RZB_SDR_C_BAD_H (0x017c) 852 #define RZB_SDR_C_BAD_L (0x0180) 853 #define RZB_SDR_C_SAD_H (0x0184) 854 #define RZB_SDR_C_SAD_L (0x0188) 855 856 #define RZB_SDR_C_PTR_S (0x0190) 857 #define RZB_SDR_C_PTR_E (0x0194) 858 859 /* Shared Bitmasks between RZA & RZB */ 860 #define RSZ_EN_EN (1 << 0) 861 862 #define RSZ_420_CEN (1 << 1) 863 #define RSZ_420_YEN (1 << 0) 864 865 #define RSZ_I_VPS_MASK (0x1fff) 866 867 #define RSZ_I_HPS_MASK (0x1fff) 868 869 #define RSZ_O_VSZ_MASK (0x1fff) 870 871 #define RSZ_O_HSZ_MASK (0x1ffe) 872 873 #define RSZ_V_PHS_Y_MASK (0x3fff) 874 875 #define RSZ_V_PHS_C_MASK (0x3fff) 876 877 #define RSZ_V_DIF_MASK (0x3fff) 878 879 #define RSZ_V_TYP_C (1 << 1) 880 #define RSZ_V_TYP_Y (1 << 0) 881 882 #define RSZ_V_LPF_C_MASK (0x3f << 6) 883 #define RSZ_V_LPF_C_SHIFT 6 884 #define RSZ_V_LPF_Y_MASK (0x3f << 0) 885 #define RSZ_V_LPF_Y_SHIFT 0 886 887 #define RSZ_H_PHS_MASK (0x3fff) 888 889 #define RSZ_H_DIF_MASK (0x3fff) 890 891 #define RSZ_H_TYP_C (1 << 1) 892 #define RSZ_H_TYP_Y (1 << 0) 893 894 #define RSZ_H_LPF_C_MASK (0x3f << 6) 895 #define RSZ_H_LPF_C_SHIFT 6 896 #define RSZ_H_LPF_Y_MASK (0x3f << 0) 897 #define RSZ_H_LPF_Y_SHIFT 0 898 899 #define RSZ_DWN_EN_DWN_EN (1 << 0) 900 901 #endif /* _OMAP4_ISS_REGS_H_ */ 902