/drivers/gpu/drm/radeon/ |
D | uvd_v2_2.c | 45 radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0)); in uvd_v2_2_fence_emit() 47 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0)); in uvd_v2_2_fence_emit() 49 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0)); in uvd_v2_2_fence_emit() 51 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0)); in uvd_v2_2_fence_emit() 54 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0)); in uvd_v2_2_fence_emit() 56 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0)); in uvd_v2_2_fence_emit() 58 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0)); in uvd_v2_2_fence_emit() 79 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_LOW, 0)); in uvd_v2_2_semaphore_emit() 82 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_HIGH, 0)); in uvd_v2_2_semaphore_emit() 85 radeon_ring_write(ring, PACKET0(UVD_SEMA_CMD, 0)); in uvd_v2_2_semaphore_emit()
|
D | uvd_v1_0.c | 87 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0)); in uvd_v1_0_fence_emit() 89 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0)); in uvd_v1_0_fence_emit() 91 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0)); in uvd_v1_0_fence_emit() 94 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0)); in uvd_v1_0_fence_emit() 96 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0)); in uvd_v1_0_fence_emit() 98 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0)); in uvd_v1_0_fence_emit() 185 tmp = PACKET0(UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); in uvd_v1_0_init() 189 tmp = PACKET0(UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); in uvd_v1_0_init() 193 tmp = PACKET0(UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); in uvd_v1_0_init() 198 radeon_ring_write(ring, PACKET0(UVD_SEMA_TIMEOUT_STATUS, 0)); in uvd_v1_0_init() [all …]
|
D | r300.c | 191 radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_TL, 0)); in r300_fence_ring_emit() 193 radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_BR, 0)); in r300_fence_ring_emit() 196 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); in r300_fence_ring_emit() 198 radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); in r300_fence_ring_emit() 201 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); in r300_fence_ring_emit() 205 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); in r300_fence_ring_emit() 208 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); in r300_fence_ring_emit() 211 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0)); in r300_fence_ring_emit() 213 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0)); in r300_fence_ring_emit() 244 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0)); in r300_ring_start() [all …]
|
D | uvd_v3_1.c | 47 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_LOW, 0)); in uvd_v3_1_semaphore_emit() 50 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_HIGH, 0)); in uvd_v3_1_semaphore_emit() 53 radeon_ring_write(ring, PACKET0(UVD_SEMA_CMD, 0)); in uvd_v3_1_semaphore_emit()
|
D | rv515.c | 70 radeon_ring_write(ring, PACKET0(ISYNC_CNTL, 0)); in rv515_ring_start() 76 radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)); in rv515_ring_start() 78 radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0)); in rv515_ring_start() 80 radeon_ring_write(ring, PACKET0(GB_SELECT, 0)); in rv515_ring_start() 82 radeon_ring_write(ring, PACKET0(GB_ENABLE, 0)); in rv515_ring_start() 84 radeon_ring_write(ring, PACKET0(R500_SU_REG_DEST, 0)); in rv515_ring_start() 86 radeon_ring_write(ring, PACKET0(VAP_INDEX_OFFSET, 0)); in rv515_ring_start() 88 radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); in rv515_ring_start() 90 radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); in rv515_ring_start() 92 radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)); in rv515_ring_start() [all …]
|
D | r200.c | 105 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); in r200_copy_dma() 113 radeon_ring_write(ring, PACKET0(0x720, 2)); in r200_copy_dma() 120 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); in r200_copy_dma()
|
D | r100.c | 841 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); in r100_ring_hdp_flush() 844 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); in r100_ring_hdp_flush() 857 radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); in r100_fence_ring_emit() 859 radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); in r100_fence_ring_emit() 862 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); in r100_fence_ring_emit() 866 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0)); in r100_fence_ring_emit() 868 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0)); in r100_fence_ring_emit() 943 radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0)); in r100_copy_blit() 945 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); in r100_copy_blit() 982 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0)); in r100_ring_start() [all …]
|
D | r420.c | 219 radeon_ring_write(ring, PACKET0(R300_CP_RESYNC_ADDR, 1)); in r420_cp_errata_init() 233 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); in r420_cp_errata_fini()
|
D | radeon_uvd.c | 707 ib.ptr[0] = PACKET0(UVD_GPCOM_VCPU_DATA0, 0); in radeon_uvd_send_msg() 709 ib.ptr[2] = PACKET0(UVD_GPCOM_VCPU_DATA1, 0); in radeon_uvd_send_msg() 711 ib.ptr[4] = PACKET0(UVD_GPCOM_VCPU_CMD, 0); in radeon_uvd_send_msg()
|
D | r300d.h | 60 #define PACKET0(reg, n) (CP_PACKET0 | \ macro
|
D | ni.c | 2511 radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2), 0)); in cayman_vm_flush() 2515 radeon_ring_write(ring, PACKET0(HDP_MEM_COHERENCY_FLUSH_CNTL, 0)); in cayman_vm_flush() 2519 radeon_ring_write(ring, PACKET0(VM_INVALIDATE_REQUEST, 0)); in cayman_vm_flush()
|
D | rv515d.h | 200 #define PACKET0(reg, n) (CP_PACKET0 | \ macro
|
D | rv770d.h | 984 #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \ macro
|
D | nid.h | 1089 #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \ macro
|
D | sid.h | 1526 #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \ macro
|
D | r100d.h | 59 #define PACKET0(reg, n) (CP_PACKET0 | \ macro
|
D | cikd.h | 1608 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ macro
|
D | evergreend.h | 1522 #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \ macro
|
D | r600d.h | 1583 #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \ macro
|
D | r600.c | 2833 radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0)); in r600_fence_ring_emit()
|