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Searched refs:PACKET3 (Results 1 – 15 of 15) sorted by relevance

/drivers/gpu/drm/radeon/
Dni.c1358 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in cayman_fence_ring_emit()
1364 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in cayman_fence_ring_emit()
1379 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0)); in cayman_ring_ib_execute()
1384 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in cayman_ring_ib_execute()
1390 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); in cayman_ring_ib_execute()
1401 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in cayman_ring_ib_execute()
1507 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); in cayman_cp_start()
1525 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in cayman_cp_start()
1531 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in cayman_cp_start()
1535 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in cayman_cp_start()
[all …]
Dcik.c3801 radeon_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in cik_ring_test()
3857 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in cik_hdp_flush_cp_ring_emit()
3886 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in cik_fence_gfx_ring_emit()
3898 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in cik_fence_gfx_ring_emit()
3925 radeon_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5)); in cik_fence_compute_ring_emit()
3956 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); in cik_semaphore_ring_emit()
3962 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); in cik_semaphore_ring_emit()
4021 radeon_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5)); in cik_copy_cpdma()
4067 radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in cik_ring_ib_execute()
4070 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); in cik_ring_ib_execute()
[all …]
Dsi.c3342 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in si_fence_ring_emit()
3345 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in si_fence_ring_emit()
3354 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in si_fence_ring_emit()
3372 radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in si_ring_ib_execute()
3375 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); in si_ring_ib_execute()
3380 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in si_ring_ib_execute()
3386 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in si_ring_ib_execute()
3393 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); in si_ring_ib_execute()
3408 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in si_ring_ib_execute()
3411 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in si_ring_ib_execute()
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Dr600.c2620 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); in r600_cp_start()
2765 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in r600_ring_test()
2803 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in r600_fence_ring_emit()
2809 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in r600_fence_ring_emit()
2817 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in r600_fence_ring_emit()
2822 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); in r600_fence_ring_emit()
2825 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in r600_fence_ring_emit()
2829 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in r600_fence_ring_emit()
2860 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); in r600_semaphore_ring_emit()
2867 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); in r600_semaphore_ring_emit()
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Dr300d.h64 #define PACKET3(op, n) (CP_PACKET3 | \ macro
Dsid.h1535 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ macro
1539 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
Devergreen.c2796 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0)); in evergreen_ring_ib_execute()
2801 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in evergreen_ring_ib_execute()
2807 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3)); in evergreen_ring_ib_execute()
2814 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); in evergreen_ring_ib_execute()
2868 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); in evergreen_cp_start()
2887 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in evergreen_cp_start()
2893 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in evergreen_cp_start()
2897 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in evergreen_cp_start()
Dcikd.h1617 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ macro
1621 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
Drv515d.h204 #define PACKET3(op, n) (CP_PACKET3 | \ macro
Drv770d.h987 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ macro
Dnid.h1098 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ macro
Dr100d.h63 #define PACKET3(op, n) (CP_PACKET3 | \ macro
Devergreend.h1531 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ macro
Dr600d.h1586 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ macro
Dr100.c921 radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8)); in r100_copy_blit()