Searched refs:PIPESTAT (Results 1 – 4 of 4) sorted by relevance
318 u32 reg = PIPESTAT(crtc->pipe); in i9xx_check_fifo_underruns()342 u32 reg = PIPESTAT(pipe); in i9xx_set_fifo_underrun_reporting()588 u32 reg = PIPESTAT(pipe); in __i915_enable_pipestat()614 u32 reg = PIPESTAT(pipe); in __i915_disable_pipestat()2055 reg = PIPESTAT(pipe); in valleyview_pipestat_irq_handler()2802 pipe_name(pipe), I915_READ(PIPESTAT(pipe))); in i915_report_and_clear_eir()3433 I915_WRITE(PIPESTAT(pipe), 0xffff); in valleyview_irq_preinstall()3503 I915_WRITE(PIPESTAT(pipe), 0xffff); in cherryview_irq_preinstall()3654 I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask); in valleyview_display_irqs_install()3655 I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask); in valleyview_display_irqs_install()[all …]
683 I915_READ(PIPESTAT(pipe))); in i915_interrupt_info()770 I915_READ(PIPESTAT(pipe))); in i915_interrupt_info()806 I915_READ(PIPESTAT(pipe))); in i915_interrupt_info()
3827 #define PIPESTAT(pipe) _PIPE2(pipe, _PIPEASTAT) macro
915 int pipestat_reg = PIPESTAT(pipe); in intel_wait_for_vblank()13712 error->pipe[i].stat = I915_READ(PIPESTAT(i)); in intel_display_capture_error_state()