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Searched refs:PLL_P2_DIVIDE_BY_4 (Results 1 – 5 of 5) sorted by relevance

/drivers/gpu/drm/gma500/
Dpsb_intel_display.c366 if (dpll & PLL_P2_DIVIDE_BY_4) in psb_intel_crtc_clock_get()
Dpsb_intel_reg.h267 #define PLL_P2_DIVIDE_BY_4 (1 << 23) /* i830, required macro
Dcdv_intel_display.c911 if (dpll & PLL_P2_DIVIDE_BY_4) in cdv_intel_crtc_clock_get()
/drivers/gpu/drm/i915/
Di915_reg.h1744 #define PLL_P2_DIVIDE_BY_4 (1 << 23) macro
Dintel_display.c5990 dpll |= PLL_P2_DIVIDE_BY_4; in i8xx_update_pll()
8927 if (dpll & PLL_P2_DIVIDE_BY_4) in i9xx_crtc_clock_get()